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| author | Jin Kyu Song <jin.kyu.song@intel.com> | 2013-11-26 17:14:07 -0800 |
|---|---|---|
| committer | Jin Kyu Song <jin.kyu.song@intel.com> | 2013-11-27 15:43:32 -0800 |
| commit | 08ae610ec96d2f07543eb0caf90ec429ddf89f32 (patch) | |
| tree | a3609ac6cf5ab441ad4a28fd80b8745767a5e5c8 /insns-iflags.pl | |
| parent | 1ab16e46731678dd965c9e1148e62c944d9c5ed6 (diff) | |
| download | nasm-08ae610ec96d2f07543eb0caf90ec429ddf89f32.tar.gz nasm-08ae610ec96d2f07543eb0caf90ec429ddf89f32.tar.bz2 nasm-08ae610ec96d2f07543eb0caf90ec429ddf89f32.zip | |
opflags: Separate vector registers into low-16 and high-16
Since only EVEX supports all 32 vector registers encoding for now,
VEX/REX encoded instructions should not take high-16 registers as operands.
This filtering had been done using instruction flag so far, but
using the opflags makes more sense.
[XYZ]MMREG operands used for non-EVEX instructions are automatically
converted to [XYZ]MM_L16 in insns.pl
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Diffstat (limited to 'insns-iflags.pl')
0 files changed, 0 insertions, 0 deletions