summaryrefslogtreecommitdiff
path: root/src/util
diff options
context:
space:
mode:
authorDave Airlie <airlied@redhat.com>2021-03-25 13:40:51 +1000
committerMarge Bot <eric+marge@anholt.net>2021-03-29 08:31:09 +0000
commitf7acdb1d1d7f817b96521bf97137eedf84b2dd03 (patch)
tree6e094d447af371a284cf8d300ebbf59628983f99 /src/util
parentb03cfad77a333fc367d8819f29b79dfd853f938f (diff)
downloadmesa-f7acdb1d1d7f817b96521bf97137eedf84b2dd03.tar.gz
mesa-f7acdb1d1d7f817b96521bf97137eedf84b2dd03.tar.bz2
mesa-f7acdb1d1d7f817b96521bf97137eedf84b2dd03.zip
st/glthread: allow for invalid L3 cache id.
If we get 0xffffffff consider L3 cache info invalid and don't continue. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4496 Fixes: d8ea5099658 ("util: completely rewrite and do AMD Zen L3 cache pinning correctly") Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9782>
Diffstat (limited to 'src/util')
-rw-r--r--src/util/u_cpu_detect.c2
-rw-r--r--src/util/u_cpu_detect.h2
2 files changed, 4 insertions, 0 deletions
diff --git a/src/util/u_cpu_detect.c b/src/util/u_cpu_detect.c
index a2403cd5658..bedb94f22ec 100644
--- a/src/util/u_cpu_detect.c
+++ b/src/util/u_cpu_detect.c
@@ -438,6 +438,8 @@ get_cpu_topology(void)
util_cpu_caps.cores_per_L3 = util_cpu_caps.nr_cpus;
util_cpu_caps.num_L3_caches = 1;
+ memset(util_cpu_caps.cpu_to_L3, 0xff, sizeof(util_cpu_caps.cpu_to_L3));
+
#if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
/* AMD Zen */
if (util_cpu_caps.family >= CPU_AMD_ZEN1_ZEN2 &&
diff --git a/src/util/u_cpu_detect.h b/src/util/u_cpu_detect.h
index ec3ef436581..1c7239b2ec7 100644
--- a/src/util/u_cpu_detect.h
+++ b/src/util/u_cpu_detect.h
@@ -105,6 +105,8 @@ struct util_cpu_caps_t {
util_affinity_mask *L3_affinity_mask;
};
+#define U_CPU_INVALID_L3 0xffff
+
static inline const struct util_cpu_caps_t *
util_get_cpu_caps(void)
{