PR middle-end/16719

	PR middle-end/18421
	* config/m68k/m68k.h (HARD_REGNO_MODE_OK): Disallow bytes
	in address registers.
	* config/m68k/m68k.c (hard_regno_mode_ok): Likewise.
	* config/m68k/m68k.md: Replace 's' with 'i' in 4th
	alternative of addsi3_5200.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@101900 138bc75d-0d04-0410-961f-82ee72b054a4

5 files changed, 50 insertions, 9 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 93f210fa97e..afe196e6202 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2005-07-12  Peter Barada  <peter@the-baradas.com>
+
+	PR middle-end/16719
+	PR middle-end/18421
+	* config/m68k/m68k.h (HARD_REGNO_MODE_OK): Disallow bytes
+	in address registers.
+	* config/m68k/m68k.c (hard_regno_mode_ok): Likewise.
+	* config/m68k/m68k.md: Replace 's' with 'i' in 4th
+	alternative of addsi3_5200.
+
 2005-07-11  Ian Lance Taylor  <ian@airs.com>
 
 	* config/mips/mips.md (ffs<mode>2): Remove.
diff --git a/gcc/config/m68k/m68k-protos.h b/gcc/config/m68k/m68k-protos.h
index 4d36b895875..028e2939c49 100644
--- a/gcc/config/m68k/m68k-protos.h
+++ b/gcc/config/m68k/m68k-protos.h
@@ -54,6 +54,7 @@ extern int valid_dbcc_comparison_p_2 (rtx, enum machine_mode);
 
 #endif /* RTX_CODE */
 
+extern bool m68k_regno_mode_ok (int, enum machine_mode);
 extern int flags_in_68881 (void);
 extern bool use_return_insn (void);
 extern void override_options (void);
diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c
index 155d354207e..2af20a480c3 100644
--- a/gcc/config/m68k/m68k.c
+++ b/gcc/config/m68k/m68k.c
@@ -3360,3 +3360,36 @@ m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
 
   return 1;
 }
+
+/* Value is true if hard register REGNO can hold a value of machine-mode MODE.
+   On the 68000, the cpu registers can hold any mode except bytes in address
+   registers, but the 68881 registers can hold only SFmode or DFmode.  */
+bool
+m68k_regno_mode_ok (int regno, enum machine_mode mode)
+{
+  if (regno < 8)
+    {
+	/* Data Registers, can hold aggregate if fits in.  */
+	if (regno + GET_MODE_SIZE (mode) / 4 <= 8)
+	  return true;
+    }
+  else if (regno < 16)
+    {
+	/* Address Registers, can't hold bytes, can hold aggregate if
+	   fits in.  */
+	if (GET_MODE_SIZE (mode) == 1)
+	  return false;
+	if (regno + GET_MODE_SIZE (mode) / 4 <= 16)
+	  return true;
+    }
+  else if (regno < 24)
+    {
+      /* FPU registers, hold float or complex float of long double or
+	   smaller.  */
+	if ((GET_MODE_CLASS (mode) == MODE_FLOAT
+	     || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
+	    && GET_MODE_UNIT_SIZE (mode) <= 12)
+	  return true;
+    }
+  return false;
+}
diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h
index e986f11ea93..5320749b464 100644
--- a/gcc/config/m68k/m68k.h
+++ b/gcc/config/m68k/m68k.h
@@ -260,15 +260,12 @@ Boston, MA 02110-1301, USA.  */
 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
   m68k_hard_regno_rename_ok (OLD_REG, NEW_REG)
 
-/* On the m68k, the cpu registers can hold any mode but the 68881 registers
-   can hold only SFmode or DFmode.  */
+/* Value is true if hard register REGNO can hold a value of machine-mode MODE.
+   On the 68000, the cpu registers can hold any mode except bytes in
+   address registers, the 68881 registers can hold only SFmode or DFmode.  */
+
 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
-  (((REGNO) < 16					\
-    && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8))	\
-   || ((REGNO) >= 16 && (REGNO) < 24				        \
-       && (GET_MODE_CLASS (MODE) == MODE_FLOAT		\
-	   || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)		\
-       && GET_MODE_UNIT_SIZE (MODE) <= 12))
+  m68k_regno_mode_ok ((REGNO), (MODE))
 
 #define MODES_TIEABLE_P(MODE1, MODE2)			\
   (! TARGET_68881					\
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 3e3f99c5cda..5c65b1c80d3 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -1851,7 +1851,7 @@
 (define_insn "*addsi3_5200"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,r")
 	(plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
-		 (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLs")))]
+		 (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLi")))]
   "TARGET_COLDFIRE"
   "* return output_addsi3 (operands);")