1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
|
/*
* Copyright (c) 2012 The WebM project authors. All Rights Reserved.
*
* Use of this source code is governed by a BSD-style license
* that can be found in the LICENSE file in the root of the source
* tree. An additional intellectual property rights grant can be found
* in the file PATENTS. All contributing project authors may
* be found in the AUTHORS file in the root of the source tree.
*/
#include "vpx_config.h"
#include "vp8_rtcd.h"
#include "vpx/vpx_integer.h"
#if HAVE_DSPR2
inline void prefetch_load_int(unsigned char *src)
{
__asm__ __volatile__ (
"pref 0, 0(%[src]) \n\t"
:
: [src] "r" (src)
);
}
__inline void vp8_copy_mem16x16_dspr2(
unsigned char *RESTRICT src,
int src_stride,
unsigned char *RESTRICT dst,
int dst_stride)
{
int r;
unsigned int a0, a1, a2, a3;
for (r = 16; r--;)
{
/* load src data in cache memory */
prefetch_load_int(src + src_stride);
/* use unaligned memory load and store */
__asm__ __volatile__ (
"ulw %[a0], 0(%[src]) \n\t"
"ulw %[a1], 4(%[src]) \n\t"
"ulw %[a2], 8(%[src]) \n\t"
"ulw %[a3], 12(%[src]) \n\t"
"sw %[a0], 0(%[dst]) \n\t"
"sw %[a1], 4(%[dst]) \n\t"
"sw %[a2], 8(%[dst]) \n\t"
"sw %[a3], 12(%[dst]) \n\t"
: [a0] "=&r" (a0), [a1] "=&r" (a1),
[a2] "=&r" (a2), [a3] "=&r" (a3)
: [src] "r" (src), [dst] "r" (dst)
);
src += src_stride;
dst += dst_stride;
}
}
__inline void vp8_copy_mem8x8_dspr2(
unsigned char *RESTRICT src,
int src_stride,
unsigned char *RESTRICT dst,
int dst_stride)
{
int r;
unsigned int a0, a1;
/* load src data in cache memory */
prefetch_load_int(src + src_stride);
for (r = 8; r--;)
{
/* use unaligned memory load and store */
__asm__ __volatile__ (
"ulw %[a0], 0(%[src]) \n\t"
"ulw %[a1], 4(%[src]) \n\t"
"sw %[a0], 0(%[dst]) \n\t"
"sw %[a1], 4(%[dst]) \n\t"
: [a0] "=&r" (a0), [a1] "=&r" (a1)
: [src] "r" (src), [dst] "r" (dst)
);
src += src_stride;
dst += dst_stride;
}
}
__inline void vp8_copy_mem8x4_dspr2(
unsigned char *RESTRICT src,
int src_stride,
unsigned char *RESTRICT dst,
int dst_stride)
{
int r;
unsigned int a0, a1;
/* load src data in cache memory */
prefetch_load_int(src + src_stride);
for (r = 4; r--;)
{
/* use unaligned memory load and store */
__asm__ __volatile__ (
"ulw %[a0], 0(%[src]) \n\t"
"ulw %[a1], 4(%[src]) \n\t"
"sw %[a0], 0(%[dst]) \n\t"
"sw %[a1], 4(%[dst]) \n\t"
: [a0] "=&r" (a0), [a1] "=&r" (a1)
: [src] "r" (src), [dst] "r" (dst)
);
src += src_stride;
dst += dst_stride;
}
}
#endif
|
