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2014-09-25CHV: Add PCIID placeholders for CHVSean V Kelley1-0/+2
Pending branding and differentiation by stepping. CHV is used generically to match libdrm and mesa identification. Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
2014-06-06debug: add g_intel_debug_option_flags for simple driver debugZhao, Halley1-2/+7
VA_INTEL_DEBUG_ASSERT decides assert() is enabled or not VA_INTEL_DEBUG_BENCH decides skipping swapbuffer in dri output (cherry picked from commit 60413182f66c44781456e827b439e98f21cfae4c)
2014-05-26Simplify some macrosXiang, Haihao1-266/+10
Now it can directly use the information in intel_device_info instead of checking the pci id. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit f1b3f83953cd5f6e39900d98b4858a7cb825dee0) Conflicts: src/gen8_post_processing.c src/i965_post_processing.c src/intel_driver.h
2014-05-26Add a new intel_device_info structureXiang, Haihao1-0/+16
To store statically known device information Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit eb014a09fde988ba3ed2d2be6e8d6f0c650d281e)
2014-04-23clean up some assert in i965_drv_video.cZhao, Halley1-0/+7
a return value is expected when assert is disabled. Signed-off-by: Zhao Halley <halley.zhao@intel.com> (cherry picked from commit 12c81227fd92fe028100af0cb32cc17b7f698b3d)
2014-04-23va: User specified tiling and stride support.Zhao, Halley1-0/+1
It is done by two VASurfaceAttrib: * one is buffer attribute described by VASurfaceAttribExternalBufferDescriptor. it covers strides and tiling or not. * another is buffer type to indicate that the buffer is allocated by va driver. VASurfaceAttribMemoryType:VA_SURFACE_ATTRIB_MEM_TYPE_VA Signed-off-by: Zhao Halley <halley.zhao@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 55e63685dc040e3855868b4d7ccb0ac8e1f66690)
2014-02-27New PCI IDs for BDWXiang, Haihao1-3/+10
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2014-02-27Initialize the 8x8 sampler for AVS on BDWZhao Yakui1-0/+2
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2014-02-27Add the PCI ids for BDWZhao Yakui1-0/+43
This is from the kernel driver. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2013-11-13Workaround for SNBXiang, Haihao1-0/+2
Backporting from d0184b5 in xf86-video-intel Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit e622ecedf169bccddc8910b45d92dbec7675441e)
2013-09-06Enable the Bay Trail platform.Zhao Halley1-1/+17
This patch adds PCI IDs for Bay Trail (sometimes called Valley View). As far as the video driver is concerned, it's very similar to Ivybridge GT1 except VP8 decoding support. (cherry picked from commit b3afeef8092dc4eb7cb73fce672ddf7a55205f34)
2013-07-01Check whether VEBOX is supported by the underlying OSXiang, Haihao1-0/+1
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit c586c80d29d8860011d95e78d1609ff3683f3cc4)
2013-06-25Revert "Make it built against the current upstream libdrm"Xiang, Haihao1-4/+0
The upstream libdrm now has supported VEBOX, hence remove the definition of I915_EXEC_VEBOX This reverts commit 6fdd5a24a5099d45a01da5a9f1337d26749898bb.
2013-06-09More reserved PCI IDs for HaswellXiang, Haihao1-3/+53
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit a9c66609b289c815b2bfc0385dc1f3bff6677125)
2013-06-09Fix Haswell GT3Xiang, Haihao1-26/+28
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 3c9e778718cb4d24695a880afb45e32cdf43a434)
2013-04-03Merge branch 'master' into stagingXiang, Haihao1-0/+1
Conflicts: NEWS configure.ac src/Makefile.am src/gen6_mfc.c src/gen6_mfd.c src/gen6_vme.c src/gen6_vme.h src/gen75_mfc.c src/gen75_mfd.c src/gen75_vme.c src/gen75_vpp_vebox.c src/gen75_vpp_vebox.h src/gen7_mfd.c src/i965_avc_bsd.c src/i965_decoder.h src/i965_decoder_utils.c src/i965_defines.h src/i965_drv_video.c src/i965_drv_video.h src/i965_encoder.c src/i965_encoder.h src/i965_output_dri.c src/i965_post_processing.c src/i965_post_processing.h src/i965_render.c src/i965_structs.h src/intel_driver.c src/object_heap.c src/shaders/post_processing/Common/AYUV_Load_16x8.asm src/shaders/post_processing/Common/AYUV_Load_16x8.inc src/shaders/post_processing/Common/Init_All_Regs.asm src/shaders/post_processing/Makefile.am src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.asm src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.inc src/shaders/post_processing/gen5_6/Common/Init_All_Regs.asm src/shaders/post_processing/gen5_6/Common/NV12_Load_8x4.asm src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.asm src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.inc src/shaders/post_processing/gen5_6/Makefile.am src/shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_avs_nv12.g6b src/shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_dn_nv12.g6b src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b src/shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_load_save_pa.g6b src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b src/shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/pa_load_save_nv12.g6b src/shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5 src/shaders/post_processing/gen5_6/pa_load_save_pl3.g6b src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b src/shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5 src/shaders/post_processing/gen5_6/pl3_load_save_pa.g6b src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5 src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b src/shaders/post_processing/gen7/EOT.g4a src/shaders/post_processing/gen7/Makefile.am src/shaders/post_processing/gen7/PA_AVS_Buf_0.g4a src/shaders/post_processing/gen7/PA_AVS_Buf_1.g4a src/shaders/post_processing/gen7/PA_AVS_Buf_2.g4a src/shaders/post_processing/gen7/PA_AVS_Buf_3.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_0.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_1.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_2.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_3.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_0.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_1.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_2.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_3.g4a src/shaders/post_processing/gen7/Save_AVS_NV12.g4a src/shaders/post_processing/gen7/Save_AVS_PA.g4a src/shaders/post_processing/gen7/Save_AVS_PL3.g4a src/shaders/post_processing/gen7/Save_AVS_RGB.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_BGRA.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL2.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL3.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VUYA.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VYUA.g4a src/shaders/post_processing/gen7/Set_Layer_0.g4a src/shaders/post_processing/gen7/VP_Setup.g4a src/shaders/vme/Makefile.am src/shaders/vme/inter_frame_haswell.asm src/shaders/vme/inter_frame_haswell.g75b src/shaders/vme/intra_frame_haswell.asm src/shaders/vme/intra_frame_haswell.g75b src/shaders/vme/vme75.inc src/shaders/vme/vme7_mpeg2.inc
2013-03-15Fix the initilization path and the termination path in reverseXiang, Haihao1-2/+3
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-03-04Update PCI IDs for Haswell CRWXiang, Haihao1-9/+9
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 82d6940694c7a650642ccb6d68bf01b70dba4dcc)
2013-03-04Update PCI IDs for Haswell CRWXiang, Haihao1-9/+9
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-12-28Add IS_SNB_GT1/IS_SNB_GT2/IS_IVB_GT1/IS_IVB_GT2 and remove IS_HSW_ULT and ↵Xiang, Haihao1-46/+52
IS_HSW_GT2_PLUS Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit bb946b7d2c97c94ac1888195ab1d5b9c59750d23)
2012-12-28Add IS_SNB_GT1/IS_SNB_GT2/IS_IVB_GT1/IS_IVB_GT2 and remove IS_HSW_ULT and ↵Xiang, Haihao1-46/+52
IS_HSW_GT2_PLUS Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-10-31VPP: Render target surface with background colorXiang, Haihao1-0/+2
Currently ignore alpha value. We will fix it once the alpha blend kernel is ready Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-10-29Make it built against the current upstream libdrmXiang, Haihao1-0/+4
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit a97403b2b9b5542aa6dd311b23b562a413abd431)
2012-10-24Make it built against the current upstream libdrmXiang, Haihao1-0/+4
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-10-23Handle the MFX change between A stepping and B-stepping for haswellZhao Yakui1-0/+1
The A0-stepping is still covered. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2012-10-23Add haswell PCI IDsGwenole Beauchesne1-1/+87
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2012-10-23Handle the MFX change between A stepping and B-stepping for haswellZhao Yakui1-0/+1
The A0-stepping is still covered. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2012-10-23Add PCI IDs for HaswellGwenole Beauchesne1-1/+87
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2012-10-08Fix build with VA-API 0.32.0.Gwenole Beauchesne1-0/+1
Add new <va/va_backend_compat.h> glue file with various utility functions and definitions to help building the driver against a previous version of libva (1.0.x for VA-API 0.32.x in particular). Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-04-13Add support for new Ivybridge chipsetXiang, Haihao1-1/+3
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 4e3a3146128c6f790c9f586c2141ae96955069cd)
2012-04-13Add support for new Ivybridge chipsetXiang, Haihao1-1/+3
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-03-29Add WARN_ONCE() helper macro.Gwenole Beauchesne1-0/+8
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com> (cherry picked from commit 2447c981a84cd9dc1eddf8e4258cef555503024f)
2012-03-18Add WARN_ONCE() helper macro.Gwenole Beauchesne1-0/+8
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-01-30Clear target surface with specified colorXiang, Haihao1-0/+2
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-01-10Avoid depending on va_backend.h for some filesXiang, Haihao1-0/+5
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-01-10Remove legacy DRI supportXiang, Haihao1-6/+0
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2011-12-07Add support for B43 chipsetXiang, Haihao1-1/+6
B43 is another 4 series chipset like G41/G45 Signed-off-by: Alexander Inyukhin <shurick@sectorb.msk.ru> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2011-08-22Moved files around.Gwenole Beauchesne1-0/+186
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