| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2014-09-25 | CHV: Add PCIID placeholders for CHV | Sean V Kelley | 1 | -0/+2 |
| 2014-06-06 | debug: add g_intel_debug_option_flags for simple driver debug | Zhao, Halley | 1 | -2/+7 |
| 2014-05-26 | Simplify some macros | Xiang, Haihao | 1 | -266/+10 |
| 2014-05-26 | Add a new intel_device_info structure | Xiang, Haihao | 1 | -0/+16 |
| 2014-04-23 | clean up some assert in i965_drv_video.c | Zhao, Halley | 1 | -0/+7 |
| 2014-04-23 | va: User specified tiling and stride support. | Zhao, Halley | 1 | -0/+1 |
| 2014-02-27 | New PCI IDs for BDW | Xiang, Haihao | 1 | -3/+10 |
| 2014-02-27 | Initialize the 8x8 sampler for AVS on BDW | Zhao Yakui | 1 | -0/+2 |
| 2014-02-27 | Add the PCI ids for BDW | Zhao Yakui | 1 | -0/+43 |
| 2013-11-13 | Workaround for SNB | Xiang, Haihao | 1 | -0/+2 |
| 2013-09-06 | Enable the Bay Trail platform. | Zhao Halley | 1 | -1/+17 |
| 2013-07-01 | Check whether VEBOX is supported by the underlying OS | Xiang, Haihao | 1 | -0/+1 |
| 2013-06-25 | Revert "Make it built against the current upstream libdrm" | Xiang, Haihao | 1 | -4/+0 |
| 2013-06-09 | More reserved PCI IDs for Haswell | Xiang, Haihao | 1 | -3/+53 |
| 2013-06-09 | Fix Haswell GT3 | Xiang, Haihao | 1 | -26/+28 |
| 2013-04-03 | Merge branch 'master' into staging | Xiang, Haihao | 1 | -0/+1 |
| 2013-03-15 | Fix the initilization path and the termination path in reverse | Xiang, Haihao | 1 | -2/+3 |
| 2013-03-04 | Update PCI IDs for Haswell CRW | Xiang, Haihao | 1 | -9/+9 |
| 2013-03-04 | Update PCI IDs for Haswell CRW | Xiang, Haihao | 1 | -9/+9 |
| 2012-12-28 | Add IS_SNB_GT1/IS_SNB_GT2/IS_IVB_GT1/IS_IVB_GT2 and remove IS_HSW_ULT and IS_... | Xiang, Haihao | 1 | -46/+52 |
| 2012-12-28 | Add IS_SNB_GT1/IS_SNB_GT2/IS_IVB_GT1/IS_IVB_GT2 and remove IS_HSW_ULT and IS_... | Xiang, Haihao | 1 | -46/+52 |
| 2012-10-31 | VPP: Render target surface with background color | Xiang, Haihao | 1 | -0/+2 |
| 2012-10-29 | Make it built against the current upstream libdrm | Xiang, Haihao | 1 | -0/+4 |
| 2012-10-24 | Make it built against the current upstream libdrm | Xiang, Haihao | 1 | -0/+4 |
| 2012-10-23 | Handle the MFX change between A stepping and B-stepping for haswell | Zhao Yakui | 1 | -0/+1 |
| 2012-10-23 | Add haswell PCI IDs | Gwenole Beauchesne | 1 | -1/+87 |
| 2012-10-23 | Handle the MFX change between A stepping and B-stepping for haswell | Zhao Yakui | 1 | -0/+1 |
| 2012-10-23 | Add PCI IDs for Haswell | Gwenole Beauchesne | 1 | -1/+87 |
| 2012-10-08 | Fix build with VA-API 0.32.0. | Gwenole Beauchesne | 1 | -0/+1 |
| 2012-04-13 | Add support for new Ivybridge chipset | Xiang, Haihao | 1 | -1/+3 |
| 2012-04-13 | Add support for new Ivybridge chipset | Xiang, Haihao | 1 | -1/+3 |
| 2012-03-29 | Add WARN_ONCE() helper macro. | Gwenole Beauchesne | 1 | -0/+8 |
| 2012-03-18 | Add WARN_ONCE() helper macro. | Gwenole Beauchesne | 1 | -0/+8 |
| 2012-01-30 | Clear target surface with specified color | Xiang, Haihao | 1 | -0/+2 |
| 2012-01-10 | Avoid depending on va_backend.h for some files | Xiang, Haihao | 1 | -0/+5 |
| 2012-01-10 | Remove legacy DRI support | Xiang, Haihao | 1 | -6/+0 |
| 2011-12-07 | Add support for B43 chipset | Xiang, Haihao | 1 | -1/+6 |
| 2011-08-22 | Moved files around. | Gwenole Beauchesne | 1 | -0/+186 |
