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2014-06-06Fix the scaling issue on IVB/HSW/BDWXiang, Haihao1-15/+15
Scaling is done on each 16x16 block. The shader for scaling might write pixels out-of-rectangle if the rectangle width/height isn't aligned to 16. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit d560387cc819a31791c2a30026473c9bd8786f07)
2014-06-06VPP: Simplify surface state setting for csc and scaling on IVB/HSW/BDWXiang, Haihao1-99/+81
v2: bpp[] is in unit of bits Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit d415357f25fc01b96592ba29ba95da9d6dc82ff3)
2014-06-06Remove unnecessary check with IS_GEN8()Xiang, Haihao1-22/+10
It is always true or false Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 42258e128f19b93aa102672d5f61eb73d9f9808f)
2014-05-26Rename HAS_PP() to HAS_VPP()Xiang, Haihao1-6/+0
Directly check the flag of has_vpp in codec_info Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 1c4d3468229797e787f4b99b0729baf90a115a1d) Conflicts: src/gen8_post_processing.c src/i965_post_processing.c
2014-05-26posst_processing_context_init()/finalize() callback functions for each platformXiang, Haihao1-2/+4
It is to reduce the usage of IS_GENxxx() as well. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 77b6a72504d917af9335ab94f6ecbefb8b087206)
2014-05-26Simplify some macrosXiang, Haihao1-9/+9
Now it can directly use the information in intel_device_info instead of checking the pci id. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit f1b3f83953cd5f6e39900d98b4858a7cb825dee0) Conflicts: src/gen8_post_processing.c src/i965_post_processing.c src/intel_driver.h
2014-04-23VPP: Set the alpha channel when doing the conversion from NV12 to RGBA on ↵Zhao Yakui1-0/+1
Ivy/Haswell/BDW Currently zero is written to alpha channel when doing the conversion from NV12 to RGBA(BGRA), which affects the following the rendering operation. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 4082c9db1eef45bc117fc151d60a178926ab9f73)
2014-04-23V3: Add 422H support.Alex wu1-1/+1
Changes between V3 to V2: 1. Add 422H support into gen8_post_processing.c, according to yakui's comments. changes between V2 and V1: 1. Rebase on staging branch. 2. Add 422H support for pp. 3. Reword the commit title. Signed-off-by: Alex wu <zhiwen.wu@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 347dd731d31dd37b242bbace744125554f2c09e7)
2014-04-23VPP: Use the VA_FOURCC_ABCD constant to replace the VA_FOURCC(A,B,C,D)Zhao Yakui1-21/+21
This is helpful to avoid the typo error when using VA_FOURCC(A, B, C, D). Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 0b9ed6ad9fbe46812d566fa31bf6d60739757a17) Conflicts: src/i965_post_processing.c
2014-04-23VPP: Fix the typo error of "VV16"Zhao Yakui1-1/+1
It should be "YV16" instead of "VV16". Thank Gwenole for capturing this typo error which is caused by the commit 2b5fad11a5c12d3c6ffbef15c02449a3b4e90b98. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit abd77ff2014322d152d723a3e8b1cba1e41b0a5f)
2014-04-23Add the csc conversion from YV16 to NV12Zhao Yakui1-0/+8
V1->V2: Follow Zhiwen's comment to handle the scenario of CSC conversion from YV16 to NV12 when the source is YV16 image instead of YV16 surface. Reviewed-by: Wind Yuan <feng.yuan@intel.com> Tested-by: Wind Yuan <feng.yuan@intel.com> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 2b5fad11a5c12d3c6ffbef15c02449a3b4e90b98)
2014-04-23Add the seperated file for Video post-processing on BDWZhao Yakui1-0/+1491
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 6e1baecded9d23b32daa8e34828b6a5d32a27c46) Conflicts: src/i965_post_processing.c
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