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2014-09-02H264_Encoding: Fix the incorrect Qp setting under CBR when slice_header is ↵Zhao Yakui1-4/+13
passed Fix the issue in https://bugs.freedesktop.org/show_bug.cgi?id=83143 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Tested-by: Sreerenj Balachandran <sreerenj.balachandran@intel.com> (cherry picked from commit eca8e0065e3a04156e0817d3a5ac14f4df39d603) Conflicts: src/gen6_mfc.c src/gen8_mfc.c
2014-06-16H264_encoding: Don't update the slice qp for CBR mode when finding packed ↵Zhao, Yakui1-2/+4
slice_header data Otherwise the slice qp is inconsistent and the encoding is incorrect. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 897527c30435202927e6cd05cd5189a710d02c91)
2014-06-16H264_Encoding: Add the support of packed slice header to be flexibleZhao, Yakui1-28/+0
Under some encoding scenario, the user hopes to generate the packed slice header data by themself and then the driver can insert the passed slice header packed data into the coded clip. 1.The VA_ENC_PACKED_HEADER_SLICE flag is exported and it is treated as optional. This is to say: if packed slice header data is passed, it will be inserted directly. If no packed slice header data is passed, the driver will help to generate it. 2.Another restriction is that the packed slice header data is inserted after the packed rawdata for one slice. That is to say: If it needs to insert the packed rawdata and slice header data, the packed rawdata will be inserted firstly(This is handled by the driver). Signed-off-by: Zhao, Yakui <yakui.zhao@intel.com> (cherry picked from commit 00111e8a8bfa67b971419b72577eaa1b9f47bc34) Conflicts: src/gen75_mfc.c src/gen8_mfc.c
2014-06-16H264_encoding: Add the support of inserting the packed raw data passed from userZhao, Yakui1-0/+4
Under some encoding scenario, the user-space application hopes that the driver can insert the passed packed rawdata into the coded clip. This is to allow the insertion of packed rawdata passed from user. As the position of packed rawdata is related with the slice. So the following restrictions are added: 1. the packed rawdata header type/data should be paired. 2. the packed rawdata data is inserted by following the passed order 3. the packed rawdata header type/data is split by using VAEncSliceParameterBuffer. That is to say: The packed rawdata for slice 0 should be passed before the first VAEncSliceParameterBuffer. After one VAEncSliceParameterBuffer is parsed, the subseuquent packed rawdata is for another new slice. The subsequent packed rawdata after the last VAEncSliceParameterBuffer is ignored. 4. it does not change the rule for the packed data of SPS/PPS/MISC type. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 974597ef64dc9a283d4787e1484a75d1610414f4) Conflicts: src/gen75_mfc.c src/gen8_mfc.c
2014-06-16Check the pointer against NULLXiang, Haihao1-0/+3
The issue is reported by Klockwork Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 80d1f89388c9cb70218cd759592d2167c8845322)
2014-02-27Avoid the duplicated macro-definition of surface sizeZhao Yakui1-0/+4
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2013-12-03H.264: Support Constrained Baseline profile instead of Baseline profileXiang, Haihao1-1/+1
GENx doesn't support FMO/ASO, so remove the support of Baseline profile for conformance testing. In addition, add the support for Constrained Baseline profile. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-11-13Encoding reuses aux_batchbuffer instead of allocating another new bufferZhao Yakui1-2/+8
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 052ce2930cd4661b7ce62902e6553eec0e2db9f1)
2013-11-13Calculate the required space of batch buffer to avoid buffer overflow in ↵Zhao Yakui1-1/+6
encoding The required size is based on the number of macroblocks and slice parameter. Then it can avoid that too large buffer is allocated or possible overflow. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 8acdfd023e50af37a5642e2517683c34accd78b0)
2013-11-13Follow the input Picture/Slice parameters to generate slice header/dataXiang, Haihao1-11/+21
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit f5a694e64d0163178c28dc25d9a3e7b9b1b5d162)
2013-11-13Pass the reference frame index in List0/1 into the PAK commandXiang, Haihao1-7/+14
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 68380a7f141bedcc0f6fbbbcee2f5e42b6ade0e0)
2013-11-13Indent the code of encodingXiang, Haihao1-2/+2
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 6ad68f55e9ba49af541a5e4d86a305bbd0f22d63)
2013-09-06Use the right wight/height to initialize the internal buffers for MPEG-2 ↵Xiang, Haihao1-3/+15
encoding Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 3ecbff585af918d96959ce791eec29be25360d91)
2013-05-09PAK encoding uses the reference list parsed from slice_param instead of ↵Zhao Yakui1-1/+1
hacked DPB Of course it still can work if the slice_param doesn't contain the valid REfPicList0/1(Hacked DPB mode). This is to be compatible with the older version of avcenc tool. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2013-05-09Unify the AVC ref frame index setting on Snb/Ivy/HSWZhao Yakui1-26/+1
This is to remove the duplicated code. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2013-04-03Merge branch 'master' into stagingXiang, Haihao1-0/+1
Conflicts: NEWS configure.ac src/Makefile.am src/gen6_mfc.c src/gen6_mfd.c src/gen6_vme.c src/gen6_vme.h src/gen75_mfc.c src/gen75_mfd.c src/gen75_vme.c src/gen75_vpp_vebox.c src/gen75_vpp_vebox.h src/gen7_mfd.c src/i965_avc_bsd.c src/i965_decoder.h src/i965_decoder_utils.c src/i965_defines.h src/i965_drv_video.c src/i965_drv_video.h src/i965_encoder.c src/i965_encoder.h src/i965_output_dri.c src/i965_post_processing.c src/i965_post_processing.h src/i965_render.c src/i965_structs.h src/intel_driver.c src/object_heap.c src/shaders/post_processing/Common/AYUV_Load_16x8.asm src/shaders/post_processing/Common/AYUV_Load_16x8.inc src/shaders/post_processing/Common/Init_All_Regs.asm src/shaders/post_processing/Makefile.am src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.asm src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.inc src/shaders/post_processing/gen5_6/Common/Init_All_Regs.asm src/shaders/post_processing/gen5_6/Common/NV12_Load_8x4.asm src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.asm src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.inc src/shaders/post_processing/gen5_6/Makefile.am src/shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_avs_nv12.g6b src/shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_dn_nv12.g6b src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b src/shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_load_save_pa.g6b src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b src/shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/pa_load_save_nv12.g6b src/shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5 src/shaders/post_processing/gen5_6/pa_load_save_pl3.g6b src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b src/shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5 src/shaders/post_processing/gen5_6/pl3_load_save_pa.g6b src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5 src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b src/shaders/post_processing/gen7/EOT.g4a src/shaders/post_processing/gen7/Makefile.am src/shaders/post_processing/gen7/PA_AVS_Buf_0.g4a src/shaders/post_processing/gen7/PA_AVS_Buf_1.g4a src/shaders/post_processing/gen7/PA_AVS_Buf_2.g4a src/shaders/post_processing/gen7/PA_AVS_Buf_3.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_0.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_1.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_2.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_3.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_0.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_1.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_2.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_3.g4a src/shaders/post_processing/gen7/Save_AVS_NV12.g4a src/shaders/post_processing/gen7/Save_AVS_PA.g4a src/shaders/post_processing/gen7/Save_AVS_PL3.g4a src/shaders/post_processing/gen7/Save_AVS_RGB.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_BGRA.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL2.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL3.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VUYA.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VYUA.g4a src/shaders/post_processing/gen7/Set_Layer_0.g4a src/shaders/post_processing/gen7/VP_Setup.g4a src/shaders/vme/Makefile.am src/shaders/vme/inter_frame_haswell.asm src/shaders/vme/inter_frame_haswell.g75b src/shaders/vme/intra_frame_haswell.asm src/shaders/vme/intra_frame_haswell.g75b src/shaders/vme/vme75.inc src/shaders/vme/vme7_mpeg2.inc
2013-03-15Silence a bunch of warningsXiang, Haihao1-42/+0
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-03-15Avoid potential buffer overflow issueXiang, Haihao1-20/+13
Warning if the slice type is wrong for encoding Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-01-17Refine mpeg2 mfc pipeline codeLi Xiaowei1-756/+12
move mpeg2 mfc code from gen6_mfc.c to gen7_mfc.c, because mpeg2 paking is not supported on gen6. Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
2013-01-17Add the bidirectional MVP to optimize the VME parameter on IvbZhao Yakui1-1/+3
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2013-01-17Packing the Intra macroblock in P/B slice for MPEG2Li Xiaowei1-17/+34
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
2013-01-17Add MPEG2 MFC pipeline for IVBLi Xiaowei1-1/+771
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
2012-11-01Warning fixesXiang, Haihao1-63/+0
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-11-01Encoding: use a separated command bufferXiang, Haihao1-3/+26
The command buffer is adaptive to the size of the frame. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-11-01Encoding: modify function to fill command into a specified batch bufferXiang, Haihao1-70/+142
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-10-31Remove the hard coded value to suppor the 4Kx4K encodingZhao Yakui1-5/+10
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2012-10-31Allow to create batchbuffer based on the expected buffer sizeZhao Yakui1-2/+2
This is to support the 4Kx4K encoding on Haswell. Otherwise the default batch buffer size can't hold the encoding command for 4Kx4K encoding. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2012-10-31Remove the dup code of XXX_mfc_avc_prepareZhao Yakui1-155/+1
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2012-10-31Remove the hard coded value to suppor the 4Kx4K encodingZhao Yakui1-10/+23
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2012-10-31Unify the XXX_free_avc_surface for media encoding/decodingZhao Yakui1-27/+12
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2012-10-23Use the common API to write avc SPS/PPS/SEI info on SNB/IVY/HSWZhao Yakui1-78/+2
This is to remove the dup code. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2012-10-23Add the common BRC API to avoid the duplicated codeZhao Yakui1-326/+4
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2012-10-23Add the separated files for media encoder on haswellZhao Yakui1-37/+0
There exist a lot of changes about the media encoder between Haswell and IvyBridge. For example: the VME programming and the corresponding general media command. To be simple, the separated files are added for Haswell. Otherwise it has to consider the complex backward compatibility. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2012-06-11silence compiler warningXiang, Haihao1-2/+1
gen6_mfc.c: In function ‘gen6_mfc_brc_init’: gen6_mfc.c:814:44: warning: initialization from incompatible pointer type [enabled by default] gen6_mfc.c: In function ‘gen6_mfc_avc_prepare’: gen6_mfc.c:1058:18: warning: unused variable ‘rate_control_mode’ [-Wunused-variable] Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-06-11Fix slice delta for CBR modeXiang, Haihao1-2/+2
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-06-11New BRC algorithm to match HRDRogozhkin, Dmitry V1-77/+290
It reduces the number of recoding as well. Signed-off-by: Rogozhkin, Dmitry V <dmitry.v.rogozhkin@intel.com>
2012-06-07Fix coded buffer size calculating for CBR modeXiang, Haihao1-39/+27
The encoded frame includes not only all macroblocks, but also PPS/SPS/Slice headers. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-06-07Fix QP setting for CBR modeXiang, Haihao1-0/+22
The QP specified in MFX_AVC_SLICE_STATE is also used as the starting QP in the first MB of a slice. In addition, add assertions for QP releated setting for 8-bit pixel bit-depth support Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Rogozhkin, Dmitry V <dmitry.v.rogozhkin@intel.com>
2012-05-31Accept packed misc data package such as SEI dataXiang, Haihao1-45/+27
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Tested-by: Dmitry Ermilov <dmitry.ermilov@intel.com>
2012-05-30Fix weight denom for implicit weight tables on SNB for encodingXiang, Haihao1-1/+12
It is the same of commit fd9c532 Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-04-25Support mixed mode for VMEXiang, Haihao1-1/+6
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-04-25Fix the filling of MFC batchbuffer for software pathXiang, Haihao1-24/+14
VME has output more macroblock messages which should be used when filling the MFC batchbuffer Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-04-23Added workaroud for CBR support in IVB.Zhou Chang1-0/+18
2012-04-19Remove hard-coded code.Xiang, Haihao1-12/+61
Istead, the MFX setting depends on the user setting parameters Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-04-06Change to none-block in CBR modeZhou Chang1-1/+1
2012-04-06Added interlace mode check, just a workaround.Zhou Chang1-2/+31
2012-04-06Expand the VME output buffer for Inter frameXiang, Haihao1-4/+4
Prepare for 32 MVs(128 bytes) and other information(32 bytes) from VME. In addition, use macros instead of magic numbers Signed-off-by :Xiang, Haihao <haihao.xiang@intel.com>
2012-03-16Fix compiler error after mergeXiang, Haihao1-2/+2
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-03-16Merge branch 'vaapi-ext' into staging-workXiang, Haihao1-13/+17
Conflicts: src/gen6_mfc.c
2012-03-16Fix VME output offset issueXiang, Haihao1-0/+3
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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