Follow the spec to make the 3D pipeline work in 48-bit addressing mode

Signed-off-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

1 files changed, 38 insertions, 0 deletions

diff --git a/src/i965_render.h b/src/i965_render.h
index 6904645..132e785 100644
--- a/src/i965_render.h
+++ b/src/i965_render.h
@@ -80,6 +80,44 @@ struct i965_render_state
     struct i965_kernel render_kernels[3];
     
     int max_wm_threads;
+
+    struct {
+        dri_bo *bo;
+        int bo_size;
+        unsigned int end_offset;
+    } instruction_state;
+
+    struct {
+        dri_bo *bo;
+    } indirect_state;
+
+    struct {
+        dri_bo *bo;
+        int bo_size;
+        unsigned int end_offset;
+    } dynamic_state;
+
+    unsigned int curbe_offset;
+    int curbe_size;
+
+    unsigned int sampler_offset;
+    int sampler_size;
+
+    unsigned int cc_viewport_offset;
+    int cc_viewport_size;
+
+    unsigned int cc_state_offset;
+    int cc_state_size;
+
+    unsigned int blend_state_offset;
+    int blend_state_size;
+  
+    unsigned int sf_clip_offset;
+    int sf_clip_size;
+
+    unsigned int scissor_offset;
+    int scissor_size;
+
 };
 
 bool i965_render_init(VADriverContextP ctx);