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authorZhao Yakui <yakui.zhao@intel.com>2012-10-31 16:47:57 +0800
committerXiang, Haihao <haihao.xiang@intel.com>2012-10-31 22:04:07 +0800
commitfb0bef337776499a1ab1926f27fd25ecd5971c5e (patch)
tree98594fcd7488f5efde37e3a0410cab5a973bda5c /src/i965_encoder.c
parent264c88a77f5794ae0b4bd886468cc7aa695c6f6b (diff)
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Allow to create batchbuffer based on the expected buffer size
This is to support the 4Kx4K encoding on Haswell. Otherwise the default batch buffer size can't hold the encoding command for 4Kx4K encoding. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Diffstat (limited to 'src/i965_encoder.c')
-rw-r--r--src/i965_encoder.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/i965_encoder.c b/src/i965_encoder.c
index b37915b..d71a59c 100644
--- a/src/i965_encoder.c
+++ b/src/i965_encoder.c
@@ -161,7 +161,7 @@ gen6_enc_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
encoder_context->base.destroy = intel_encoder_context_destroy;
encoder_context->base.run = intel_encoder_end_picture;
- encoder_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
+ encoder_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
encoder_context->rate_control_mode = VA_RC_NONE;
for (i = 0; i < obj_config->num_attribs; i++) {
@@ -193,7 +193,7 @@ gen7_enc_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
encoder_context->base.destroy = intel_encoder_context_destroy;
encoder_context->base.run = intel_encoder_end_picture;
- encoder_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
+ encoder_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
encoder_context->input_yuv_surface = VA_INVALID_SURFACE;
encoder_context->is_tmp_id = 0;
encoder_context->rate_control_mode = VA_RC_NONE;
@@ -227,7 +227,7 @@ gen75_enc_hw_context_init(VADriverContextP ctx, struct object_config *obj_config
encoder_context->base.destroy = intel_encoder_context_destroy;
encoder_context->base.run = intel_encoder_end_picture;
- encoder_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
+ encoder_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
encoder_context->input_yuv_surface = VA_INVALID_SURFACE;
encoder_context->is_tmp_id = 0;
encoder_context->rate_control_mode = VA_RC_NONE;