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| author | Zhao Yakui <yakui.zhao@intel.com> | 2014-09-01 15:48:42 +0800 |
|---|---|---|
| committer | Zhao, Yakui <yakui.zhao@intel.com> | 2014-09-02 09:10:59 +0800 |
| commit | 865f288d6821dfea5a9dc2a0525eba69ef786b23 (patch) | |
| tree | 66f201044ea91a7468db0f589c4780300baf1504 /src/gen8_mfc.c | |
| parent | f3f49f2f0e6b3669d9b09341a11cf0b96e138674 (diff) | |
| download | libva-intel-driver-865f288d6821dfea5a9dc2a0525eba69ef786b23.tar.gz libva-intel-driver-865f288d6821dfea5a9dc2a0525eba69ef786b23.tar.bz2 libva-intel-driver-865f288d6821dfea5a9dc2a0525eba69ef786b23.zip | |
H264_Encoding: Fix the incorrect Qp setting under CBR when slice_header is passed
Fix the issue in
https://bugs.freedesktop.org/show_bug.cgi?id=83143
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Tested-by: Sreerenj Balachandran <sreerenj.balachandran@intel.com>
(cherry picked from commit eca8e0065e3a04156e0817d3a5ac14f4df39d603)
Conflicts:
src/gen6_mfc.c
src/gen8_mfc.c
Diffstat (limited to 'src/gen8_mfc.c')
| -rw-r--r-- | src/gen8_mfc.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/src/gen8_mfc.c b/src/gen8_mfc.c index e3f07ad..2d76816 100644 --- a/src/gen8_mfc.c +++ b/src/gen8_mfc.c @@ -1032,12 +1032,15 @@ gen8_mfc_avc_pipeline_slice_programing(VADriverContextP ctx, unsigned int tail_data[] = { 0x0, 0x0 }; int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type); int is_intra = slice_type == SLICE_TYPE_I; + int qp_slice; - + qp_slice = qp; if (rate_control_mode == VA_RC_CBR) { qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY; - if (encode_state->slice_header_index[slice_index] == 0) + if (encode_state->slice_header_index[slice_index] == 0) { pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp; + qp_slice = qp; + } } /* only support for 8-bit pixel bit-depth */ @@ -1050,7 +1053,7 @@ gen8_mfc_avc_pipeline_slice_programing(VADriverContextP ctx, pPicParameter, pSliceParameter, encode_state, encoder_context, - (rate_control_mode == VA_RC_CBR), qp, slice_batch); + (rate_control_mode == VA_RC_CBR), qp_slice, slice_batch); if ( slice_index == 0) intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch); @@ -1403,11 +1406,15 @@ gen8_mfc_avc_batchbuffer_slice(VADriverContextP ctx, int old_used = intel_batchbuffer_used_size(slice_batch), used; unsigned short head_size, tail_size; int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type); + int qp_slice; + qp_slice = qp; if (rate_control_mode == VA_RC_CBR) { qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY; - if (encode_state->slice_header_index[slice_index] == 0) + if (encode_state->slice_header_index[slice_index] == 0) { pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp; + qp_slice = qp; + } } /* only support for 8-bit pixel bit-depth */ @@ -1423,7 +1430,7 @@ gen8_mfc_avc_batchbuffer_slice(VADriverContextP ctx, encode_state, encoder_context, (rate_control_mode == VA_RC_CBR), - qp, + qp_slice, slice_batch); if (slice_index == 0) |