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authorZhou Chang <chang.zhou@intel.com>2012-04-06 15:57:40 +0800
committerXiang, Haihao <haihao.xiang@intel.com>2012-04-06 16:07:02 +0800
commitb3c9a5fb485b82eb228e9a7e6609323ec9fcd8d5 (patch)
tree71f0a3e9dce7b507e3eb17ce435b7201e1c26726
parenta737cc1f37cb74cb5a08387edb026e7043f3fd1a (diff)
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Change to none-block in CBR mode
-rw-r--r--src/gen6_mfc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gen6_mfc.c b/src/gen6_mfc.c
index eb2ab96..c9648cf 100644
--- a/src/gen6_mfc.c
+++ b/src/gen6_mfc.c
@@ -1679,8 +1679,8 @@ gen6_mfc_avc_encode_picture(VADriverContextP ctx,
/*Programing bcs pipeline*/
gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context); //filling the pipeline
gen6_mfc_run(ctx, encode_state, encoder_context);
- gen6_mfc_stop(ctx, encode_state, encoder_context, &current_frame_bits_size);
if ( rate_control_mode == VA_RC_CBR) {
+ gen6_mfc_stop(ctx, encode_state, encoder_context, &current_frame_bits_size);
//gen6_mfc_hrd_context_check(encode_state, mfc_context);
if ( gen6_mfc_bit_rate_control_context_update( encode_state, mfc_context, current_frame_bits_size) ) {
gen6_mfc_hrd_context_update(encode_state, mfc_context);