Fixed 1080p issue and add transform 8x8 support.

6 files changed, 13 insertions, 6 deletions

diff --git a/src/gen6_mfc.c b/src/gen6_mfc.c
index 37d73ee..ab48397 100644
--- a/src/gen6_mfc.c
+++ b/src/gen6_mfc.c
@@ -298,6 +298,7 @@ gen6_mfc_avc_img_state(VADriverContextP ctx,struct encode_state *encode_state,
     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
+    VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 
@@ -328,7 +329,7 @@ gen6_mfc_avc_img_state(VADriverContextP ctx,struct encode_state *encode_state,
                   (0 << 6)  |   /*Only valid for VLD decoding mode*/
                   (0 << 5)  |   /*Constrained Intra Predition Flag, from PPS*/
                   (pSequenceParameter->direct_8x8_inference_flag << 4)  |   /*Direct 8x8 inference flag*/
-                  (0 << 3)  |   /*Only 8x8 IDCT Transform Mode Flag*/
+                  (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3)  |   /*8x8 or 4x4 IDCT Transform Mode Flag*/
                   (1 << 2)  |   /*Frame MB only flag*/
                   (0 << 1)  |   /*MBAFF mode is in active*/
                   (0 << 0) );   /*Field picture flag*/
@@ -817,7 +818,7 @@ static void gen6_mfc_init(VADriverContextP ctx, struct gen6_encoder_context *gen
     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
     bo = dri_bo_alloc(i965->intel.bufmgr,
                       "Buffer",
-                      8*9600,
+                      128*128*16,
                       64);
     assert(bo);
     mfc_context->macroblock_status_buffer.bo = bo;
diff --git a/src/gen6_vme.c b/src/gen6_vme.c
index bcfbee5..a979dc8 100644
--- a/src/gen6_vme.c
+++ b/src/gen6_vme.c
@@ -786,8 +786,9 @@ static int gen6_vme_media_object(VADriverContextP ctx,
     struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
     struct object_surface *obj_surface = SURFACE(encode_state->current_render_target);
+    VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
     int mb_width = ALIGN(obj_surface->orig_width, 16) / 16;
-    int len_in_dowrds = 6 + 1;
+    int len_in_dowrds = 6 + 2;      /*6 + n: n is number of inline data*/
 
     BEGIN_BATCH(batch, len_in_dowrds);
     
@@ -800,6 +801,8 @@ static int gen6_vme_media_object(VADriverContextP ctx,
    
     /*inline data */
     OUT_BATCH(batch, mb_width << 16 | mb_y << 8 | mb_x);			/*M0.0 Refrence0 X,Y, not used in Intra*/
+    OUT_BATCH(batch, pPicParameter->pic_fields.bits.transform_8x8_mode_flag);   /* Enabling or disabling 8x8,4x4 Intra mode,
+                                                                                   more control flags will added here.*/
     ADVANCE_BATCH(batch);
 
     return len_in_dowrds * 4;
diff --git a/src/shaders/vme/gen6_vme_header.inc b/src/shaders/vme/gen6_vme_header.inc
index 5e27fa7..e689ef6 100644
--- a/src/shaders/vme/gen6_vme_header.inc
+++ b/src/shaders/vme/gen6_vme_header.inc
@@ -96,6 +96,7 @@ define(`w_in_mb_uw',            `inline_reg0.2')
 define(`orig_xy_ub',            `inline_reg0.0')
 define(`orig_x_ub',             `inline_reg0.0')    /* in macroblock */    
 define(`orig_y_ub',             `inline_reg0.1')
+define(`transform_8x8_ub',      `inline_reg0.4')
 
 /*
  * GRF 6~11 -- reserved
diff --git a/src/shaders/vme/intra_frame.asm b/src/shaders/vme/intra_frame.asm
index 809b5f3..9642c87 100644
--- a/src/shaders/vme/intra_frame.asm
+++ b/src/shaders/vme/intra_frame.asm
@@ -51,7 +51,8 @@ mov  (1) tmp_reg0.20<1>:UB      thread_id_ub {align1};                  /* dispa
 mov  (8) vme_msg_0.0<1>:UD      tmp_reg0.0<8,8,1>:UD {align1};
 
 /* m1 */
-mov  (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE + LUMA_INTRA_4x4_DISABLE {align1};
+cmp.nz.f0.0 (1) null<1>:UW transform_8x8_ub<0,1,0>:UB 1:UW {align1};
+(f0.0) mov  (1) intra_part_mask_ub<1>:UB  LUMA_INTRA_8x8_DISABLE + LUMA_INTRA_4x4_DISABLE {align1};
 
 cmp.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB 0:UW {align1};                                                   /* X != 0 */
 (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_AE {align1};         /* A */
diff --git a/src/shaders/vme/intra_frame.g6b b/src/shaders/vme/intra_frame.g6b
index 90ee252..82a3e4b 100644
--- a/src/shaders/vme/intra_frame.g6b
+++ b/src/shaders/vme/intra_frame.g6b
@@ -16,7 +16,8 @@
    { 0x00200041, 0x24082e29, 0x004500a0, 0x00100010 },
    { 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
    { 0x00600001, 0x20000022, 0x008d0400, 0x00000000 },
-   { 0x00000001, 0x243c00f1, 0x00000000, 0x00000006 },
+   { 0x02000010, 0x20002e28, 0x000000a4, 0x00010001 },
+   { 0x00010001, 0x243c00f1, 0x00000000, 0x00000006 },
    { 0x02000010, 0x20002e28, 0x000000a0, 0x00000000 },
    { 0x00010040, 0x243d1e31, 0x0000043d, 0x00000060 },
    { 0x02000010, 0x20002e28, 0x000000a1, 0x00000000 },
diff --git a/src/shaders/vme/intra_frame.g7b b/src/shaders/vme/intra_frame.g7b
index cc063d8..74218ff 100644
--- a/src/shaders/vme/intra_frame.g7b
+++ b/src/shaders/vme/intra_frame.g7b
@@ -16,7 +16,7 @@
    { 0x00200041, 0x24082e29, 0x004500a0, 0x00100010 },
    { 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
    { 0x00600001, 0x28000021, 0x008d0400, 0x00000000 },
-   { 0x00000001, 0x243c00f1, 0x00000000, 0x00000006 },
+   { 0x00010001, 0x243c00f1, 0x00000000, 0x00000006 },
    { 0x02000010, 0x20002e28, 0x000000a0, 0x00000000 },
    { 0x00010040, 0x243d1e31, 0x0000043d, 0x00000060 },
    { 0x02000010, 0x20002e28, 0x000000a1, 0x00000000 },