Directly use the size of the output MV from VME to format MFC_AVC_PAK_OBJECT command

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

7 files changed, 71 insertions, 16 deletions

diff --git a/src/shaders/utils/mfc_batchbuffer_avc_inter.asm b/src/shaders/utils/mfc_batchbuffer_avc_inter.asm
index bc8e154..1cf4502 100644
--- a/src/shaders/utils/mfc_batchbuffer_avc_inter.asm
+++ b/src/shaders/utils/mfc_batchbuffer_avc_inter.asm
@@ -39,8 +39,7 @@ __PAK_OBJECT:
         mov             (16)    pak_object_ud<1>:ud             0x0:ud {align1} ;
         /* DW0 */
         mov             (1)     pak_object0_ud<1>:ud            MFC_AVC_PAK_OBJECT_INTER_DW0 ;
-        /* DW1 */
-        mov             (1)     pak_object1_ud<1>:ud            MFC_AVC_PAK_OBJECT_INTER_DW1 ;
+        
         /* DW2 */
         mul             (1)     pak_object2_ud<1>:ud            tmp_offset.0<0,1,0>:ud          INTER_VME_OUTPUT_IN_BYTES:ud {align1} ;
         
@@ -68,9 +67,11 @@ send (16)
         rlen ob_read_wb_len_vme_inter
         {align1};
 
+        /* DW1 must be 32 for 8 MVs and 128 for 32 MVs !!! */
+        mov             (1)     pak_object1_ud<1>:ud            ob_read_wb0.8<0,1,0>:ud {align1} ;
+        
         /* DW3 */
-        and             (1)     pak_object3_ud<1>:ud            ob_read_wb0.0<0,1,0>:ud         0xFFFF {align1} ;
-        add             (1)     pak_object3_ud<1>:ud            pak_object3_ud<0,1,0>:ud        MFC_AVC_PAK_OBJECT_INTER_DW3 {align1} ;
+        mov             (1)     pak_object3_ud<1>:ud            ob_read_wb0.0<0,1,0>:ud {align1} ;
         
         /* DW4 */
         add             (1)     pak_object4_ud<1>:ud            mb_xy<0,1,0>:uw                 MFC_AVC_PAK_OBJECT_INTER_DW4 {align1} ;
diff --git a/src/shaders/utils/mfc_batchbuffer_avc_inter.g6b b/src/shaders/utils/mfc_batchbuffer_avc_inter.g6b
index 113d0e5..b88bfca 100644
--- a/src/shaders/utils/mfc_batchbuffer_avc_inter.g6b
+++ b/src/shaders/utils/mfc_batchbuffer_avc_inter.g6b
@@ -21,14 +21,13 @@
    { 0x00000040, 0x21082c21, 0x00000108, 0x00080008 },
    { 0x00800001, 0x23400061, 0x00000000, 0x00000000 },
    { 0x00000001, 0x23400061, 0x00000000, 0x71490009 },
-   { 0x00000001, 0x23440061, 0x00000000, 0x00000020 },
    { 0x00000041, 0x23480c21, 0x000001e0, 0x000000a0 },
    { 0x00000001, 0x23540061, 0x00000000, 0x000f000f },
    { 0x01000005, 0x20002d28, 0x020000ac, 0x00020002 },
    { 0x00600001, 0x20000022, 0x008d0100, 0x00000000 },
    { 0x05800031, 0x22001cc9, 0x00000000, 0x022a0200 },
-   { 0x00000005, 0x234c1c21, 0x00000200, 0x0000ffff },
-   { 0x00000040, 0x234c0c21, 0x0000034c, 0x014e0000 },
+   { 0x00000001, 0x23440021, 0x00000208, 0x00000000 },
+   { 0x00000001, 0x234c0021, 0x00000200, 0x00000000 },
    { 0x00000040, 0x23500d21, 0x000000b0, 0xffff0000 },
    { 0x00000040, 0x20b02e31, 0x000000b0, 0x00010001 },
    { 0x01000010, 0x20004528, 0x000000b4, 0x000000b0 },
diff --git a/src/shaders/utils/mfc_batchbuffer_avc_inter.g7b b/src/shaders/utils/mfc_batchbuffer_avc_inter.g7b
index 871e580..be910ba 100644
--- a/src/shaders/utils/mfc_batchbuffer_avc_inter.g7b
+++ b/src/shaders/utils/mfc_batchbuffer_avc_inter.g7b
@@ -21,14 +21,13 @@
    { 0x00000040, 0x21082c21, 0x00000108, 0x00080008 },
    { 0x00800001, 0x23400061, 0x00000000, 0x00000000 },
    { 0x00000001, 0x23400061, 0x00000000, 0x71490009 },
-   { 0x00000001, 0x23440061, 0x00000000, 0x00000020 },
    { 0x00000041, 0x23480c21, 0x000001e0, 0x000000a0 },
    { 0x00000001, 0x23540061, 0x00000000, 0x000f000f },
    { 0x01000005, 0x20002d28, 0x020000ac, 0x00020002 },
    { 0x00600001, 0x28000021, 0x008d0100, 0x00000000 },
    { 0x0a800031, 0x22001ca9, 0x00000800, 0x02280200 },
-   { 0x00000005, 0x234c1c21, 0x00000200, 0x0000ffff },
-   { 0x00000040, 0x234c0c21, 0x0000034c, 0x014e0000 },
+   { 0x00000001, 0x23440021, 0x00000208, 0x00000000 },
+   { 0x00000001, 0x234c0021, 0x00000200, 0x00000000 },
    { 0x00000040, 0x23500d21, 0x000000b0, 0xffff0000 },
    { 0x00000040, 0x20b02e31, 0x000000b0, 0x00010001 },
    { 0x01000010, 0x20004528, 0x000000b4, 0x000000b0 },
diff --git a/src/shaders/vme/inter_frame.asm b/src/shaders/vme/inter_frame.asm
index 5a74468..a808cf3 100644
--- a/src/shaders/vme/inter_frame.asm
+++ b/src/shaders/vme/inter_frame.asm
@@ -116,9 +116,23 @@ send (16)
         {align1};
 
 /* other info */        
-add             (1)     msg_reg0.8<1>:UD        obw_m0.8<0,1,0>:UD      INTER_VME_OUTPUT_MV_IN_OWS:UD {align1} ;        
-mov             (1)     msg_reg1.0<1>:UD        vme_wb0.0<0,1,0>:UD     {align1};
+add             (1)     msg_reg0.8<1>:UD        obw_m0.8<0,1,0>:UD      INTER_VME_OUTPUT_MV_IN_OWS:UD {align1} ;
+
+mov             (1)     tmp_uw1<1>:uw           0:uw {align1} ;
+mov             (1)     tmp_ud1<1>:ud           0:ud {align1} ;
+and.z.f0.0      (1)     null<1>:ud              vme_wb0.0<0,1,0>:ud     INTRAMBFLAG_MASK:ud {align1} ;
+(f0.0)and       (1)     tmp_uw1<1>:uw           vme_wb0.2<0,1,0>:uw     MVSIZE_UW_MASK:uw {align1} ;
+(f0.0)shr       (1)     tmp_ud1<1>:ud           tmp_uw1<1>:uw           4:w {align1} ;
+(f0.0)mul       (1)     tmp_ud1<1>:ud           tmp_ud1<0,1,0>:ud       96:ud {align1} ;
+(f0.0)add       (1)     tmp_ud1<1>:ud           tmp_ud1<0,1,0>:ud       32:uw {align1} ;
+(f0.0)shl       (1)     tmp_uw1<1>:uw           tmp_uw1<0,1,0>:uw       1:uw {align1} ;
+(f0.0)add       (1)     tmp_uw1<1>:uw           tmp_uw1<0,1,0>:uw       MVSIZE_UW_BASE:uw {align1} ;
+add             (1)     tmp_uw1<1>:uw           tmp_uw1<0,1,0>:uw       CBP_DC_YUV_UW:uw {align1} ;
+
+mov             (1)     msg_reg1.0<1>:uw        vme_wb0.0<0,1,0>:uw     {align1} ;
+mov             (1)     msg_reg1.2<1>:uw        tmp_uw1<0,1,0>:uw       {align1} ;
 mov             (1)     msg_reg1.4<1>:UD        vme_wb0.28<0,1,0>:UD    {align1};
+mov             (1)     msg_reg1.8<1>:ud        tmp_ud1<0,1,0>:ud       {align1} ;
         
 /* bind index 3, write 1 oword, msg type: 8(OWord Block Write) */
 send (16)
diff --git a/src/shaders/vme/inter_frame.g6b b/src/shaders/vme/inter_frame.g6b
index 373e44f..82a6e91 100644
--- a/src/shaders/vme/inter_frame.g6b
+++ b/src/shaders/vme/inter_frame.g6b
@@ -29,8 +29,20 @@
    { 0x00600001, 0x20400022, 0x008d04a0, 0x00000000 },
    { 0x05800031, 0x22001cdd, 0x00000000, 0x0a1b0403 },
    { 0x00000040, 0x20080c22, 0x00000488, 0x00000008 },
-   { 0x00000001, 0x20200022, 0x00000180, 0x00000000 },
+   { 0x00000001, 0x24e20169, 0x00000000, 0x00000000 },
+   { 0x00000001, 0x24e40061, 0x00000000, 0x00000000 },
+   { 0x01000005, 0x20000c20, 0x00000180, 0x00002000 },
+   { 0x00010005, 0x24e22d29, 0x00000182, 0x00700070 },
+   { 0x00010008, 0x24e43d21, 0x002004e2, 0x00040004 },
+   { 0x00010041, 0x24e40c21, 0x000004e4, 0x00000060 },
+   { 0x00010040, 0x24e42c21, 0x000004e4, 0x00200020 },
+   { 0x00010009, 0x24e22d29, 0x000004e2, 0x00010001 },
+   { 0x00010040, 0x24e22d29, 0x000004e2, 0x00400040 },
+   { 0x00000040, 0x24e22d29, 0x000004e2, 0x000e000e },
+   { 0x00000001, 0x2020012a, 0x00000180, 0x00000000 },
+   { 0x00000001, 0x2022012a, 0x000004e2, 0x00000000 },
    { 0x00000001, 0x20240022, 0x0000019c, 0x00000000 },
+   { 0x00000001, 0x20280022, 0x000004e4, 0x00000000 },
    { 0x05800031, 0x22001cdd, 0x00000000, 0x041b0003 },
    { 0x00000040, 0x20a02e31, 0x000000a0, 0x00010001 },
    { 0x00000040, 0x24482d29, 0x00000448, 0x00100010 },
@@ -43,6 +55,6 @@
    { 0x00010040, 0x24423dad, 0x00000442, 0x00100010 },
    { 0x00000040, 0x24882c21, 0x00000488, 0x000a000a },
    { 0x01000040, 0x20a63dad, 0x020000a6, 0xffffffff },
-   { 0x00110020, 0x34001c00, 0x02001400, 0xffffffc6 },
+   { 0x00110020, 0x34001c00, 0x02001400, 0xffffffae },
    { 0x00600001, 0x20000022, 0x008d0000, 0x00000000 },
    { 0x07800031, 0x24001cc8, 0x00000000, 0x82000010 },
diff --git a/src/shaders/vme/inter_frame.g7b b/src/shaders/vme/inter_frame.g7b
index 190c204..6be71a8 100644
--- a/src/shaders/vme/inter_frame.g7b
+++ b/src/shaders/vme/inter_frame.g7b
@@ -26,8 +26,20 @@
    { 0x00600001, 0x28400021, 0x008d04a0, 0x00000000 },
    { 0x0a800031, 0x20001cac, 0x00000800, 0x0a0a0403 },
    { 0x00000040, 0x28080c21, 0x00000488, 0x00000008 },
-   { 0x00000001, 0x28200021, 0x00000180, 0x00000000 },
+   { 0x00000001, 0x24e20169, 0x00000000, 0x00000000 },
+   { 0x00000001, 0x24e40061, 0x00000000, 0x00000000 },
+   { 0x01000005, 0x20000c20, 0x00000180, 0x00002000 },
+   { 0x00010005, 0x24e22d29, 0x00000182, 0x00700070 },
+   { 0x00010008, 0x24e43d21, 0x002004e2, 0x00040004 },
+   { 0x00010041, 0x24e40c21, 0x000004e4, 0x00000060 },
+   { 0x00010040, 0x24e42c21, 0x000004e4, 0x00200020 },
+   { 0x00010009, 0x24e22d29, 0x000004e2, 0x00010001 },
+   { 0x00010040, 0x24e22d29, 0x000004e2, 0x00400040 },
+   { 0x00000040, 0x24e22d29, 0x000004e2, 0x000e000e },
+   { 0x00000001, 0x28200129, 0x00000180, 0x00000000 },
+   { 0x00000001, 0x28220129, 0x000004e2, 0x00000000 },
    { 0x00000001, 0x28240021, 0x0000019c, 0x00000000 },
+   { 0x00000001, 0x28280021, 0x000004e4, 0x00000000 },
    { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0003 },
    { 0x00000040, 0x20a02e31, 0x000000a0, 0x00010001 },
    { 0x00000040, 0x24482d29, 0x00000448, 0x00100010 },
@@ -37,6 +49,6 @@
    { 0x00010040, 0x244a2d29, 0x0000044a, 0x00100010 },
    { 0x00000040, 0x24882c21, 0x00000488, 0x000a000a },
    { 0x01000040, 0x20a63dad, 0x020000a6, 0xffffffff },
-   { 0x00110020, 0x34001c00, 0x02001400, 0xffffffd0 },
+   { 0x00110020, 0x34001c00, 0x02001400, 0xffffffb8 },
    { 0x00600001, 0x28000021, 0x008d0000, 0x00000000 },
    { 0x07800031, 0x24001ca8, 0x00000800, 0x82000010 },
diff --git a/src/shaders/vme/vme.inc b/src/shaders/vme/vme.inc
index 09b4e19..cf1069a 100644
--- a/src/shaders/vme/vme.inc
+++ b/src/shaders/vme/vme.inc
@@ -68,6 +68,11 @@ define(`INTRA_PREDICTORE_MODE',         `0x11111111:UD')
 define(`INTER_VME_OUTPUT_IN_OWS',       `10')
 define(`INTER_VME_OUTPUT_MV_IN_OWS',    `8')
 
+define(`INTRAMBFLAG_MASK',              `0x00002000')
+define(`MVSIZE_UW_MASK',                `0x0070')
+define(`MVSIZE_UW_BASE',                `0x0040')
+define(`CBP_DC_YUV_UW',                 `0x000E')
+
 #ifdef DEV_SNB
 
 define(`OBW_CACHE_TYPE',                `5')
@@ -186,6 +191,19 @@ define(`tmp_reg5',              `r37')
 define(`obw_m1',                `tmp_reg5')
 define(`tmp_reg6',              `r38')
 define(`tmp_x_w',               `tmp_reg6.0')
+define(`tmp_reg7',              `r39')
+define(`tmp_ud0',               `tmp_reg7.0')
+define(`tmp_ud1',               `tmp_reg7.4')
+define(`tmp_ud2',               `tmp_reg7.8')
+define(`tmp_ud3',               `tmp_reg7.12')
+define(`tmp_uw0',               `tmp_reg7.0')
+define(`tmp_uw1',               `tmp_reg7.2')
+define(`tmp_uw2',               `tmp_reg7.4')
+define(`tmp_uw3',               `tmp_reg7.6')
+define(`tmp_uw4',               `tmp_reg7.8')
+define(`tmp_uw5',               `tmp_reg7.10')
+define(`tmp_uw6',               `tmp_reg7.12')
+define(`tmp_uw7',               `tmp_reg7.14')
 
 /*
  * MRF registers