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author | Xiang, Haihao <haihao.xiang@intel.com> | 2015-03-16 10:00:07 +0800 |
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committer | Xiang, Haihao <haihao.xiang@intel.com> | 2015-03-16 13:18:10 +0800 |
commit | 5f0c004ff8272d5d02e50cf13417bf0d9450d39d (patch) | |
tree | e89ab01601ec8b665216e37121a0021086c7fba6 | |
parent | 5e3f04d61d407581e9f3828161784a6f4c6d83c3 (diff) | |
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Add new SKL PCI ids
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit b4777133a1e87a8b75df8366c0d72b544ae4794e)
-rw-r--r-- | src/i965_pciids.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/i965_pciids.h b/src/i965_pciids.h index 22b8215..22a43b1 100644 --- a/src/i965_pciids.h +++ b/src/i965_pciids.h @@ -135,16 +135,23 @@ CHIPSET(0x22B2, chv, chv, "Intel(R) CherryView") CHIPSET(0x22B3, chv, chv, "Intel(R) CherryView") CHIPSET(0x1902, skl, skl, "Intel(R) Skylake") CHIPSET(0x1906, skl, skl, "Intel(R) Skylake") +CHIPSET(0x190A, skl, skl, "Intel(R) Skylake") +CHIPSET(0x190B, skl, skl, "Intel(R) Skylake") CHIPSET(0x190E, skl, skl, "Intel(R) Skylake") CHIPSET(0x1912, skl, skl, "Intel(R) Skylake") CHIPSET(0x1913, skl, skl, "Intel(R) Skylake") CHIPSET(0x1915, skl, skl, "Intel(R) Skylake") CHIPSET(0x1916, skl, skl, "Intel(R) Skylake") CHIPSET(0x1917, skl, skl, "Intel(R) Skylake") +CHIPSET(0x191A, skl, skl, "Intel(R) Skylake") CHIPSET(0x191B, skl, skl, "Intel(R) Skylake") +CHIPSET(0x191D, skl, skl, "Intel(R) Skylake") CHIPSET(0x191E, skl, skl, "Intel(R) Skylake") CHIPSET(0x1921, skl, skl, "Intel(R) Skylake") CHIPSET(0x1926, skl, skl, "Intel(R) Skylake") +CHIPSET(0x192A, skl, skl, "Intel(R) Skylake") CHIPSET(0x192B, skl, skl, "Intel(R) Skylake") +CHIPSET(0x1932, skl, skl, "Intel(R) Skylake") CHIPSET(0x193A, skl, skl, "Intel(R) Skylake") CHIPSET(0x193B, skl, skl, "Intel(R) Skylake") +CHIPSET(0x193D, skl, skl, "Intel(R) Skylake") |