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authorKen Wang <Qingqing.Wang@amd.com>2015-06-03 17:15:29 +0800
committerAlex Deucher <alexander.deucher@amd.com>2015-08-05 13:47:50 -0400
commit4bf29413a3e4da9fdabfd8d145702bc6922b0d72 (patch)
treedd6c3e6341a94385e0d606d5b4d336398e01987b /include
parentfc9fc7dd1145dd573d051dfe9ab6d495f69b5865 (diff)
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amdgpu: add vram_type and vram_bit_width for interface query
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Diffstat (limited to 'include')
-rw-r--r--include/drm/amdgpu_drm.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 4d96bcf0..772f8032 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -540,6 +540,15 @@ struct drm_amdgpu_info_firmware {
uint32_t feature;
};
+#define AMDGPU_VRAM_TYPE_UNKNOWN 0
+#define AMDGPU_VRAM_TYPE_GDDR1 1
+#define AMDGPU_VRAM_TYPE_DDR2 2
+#define AMDGPU_VRAM_TYPE_GDDR3 3
+#define AMDGPU_VRAM_TYPE_GDDR4 4
+#define AMDGPU_VRAM_TYPE_GDDR5 5
+#define AMDGPU_VRAM_TYPE_HBM 6
+#define AMDGPU_VRAM_TYPE_DDR3 7
+
struct drm_amdgpu_info_device {
/** PCI Device ID */
uint32_t device_id;
@@ -573,6 +582,10 @@ struct drm_amdgpu_info_device {
/** Page table entry - fragment size */
uint32_t pte_fragment_size;
uint32_t gart_page_size;
+ /** video memory type information*/
+ uint32_t vram_type;
+ /** video memory bit width*/
+ uint32_t vram_bit_width;
};
struct drm_amdgpu_info_hw_ip {