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author | Ken Wang <Qingqing.Wang@amd.com> | 2015-07-10 22:22:27 +0800 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2015-08-05 13:47:52 -0400 |
commit | 926c80568691e04abdfcd21b6e9be61331e95b03 (patch) | |
tree | bc358b99874cfc930c8e3853b9d3db3f7b4ecee9 /amdgpu/amdgpu.h | |
parent | 01e4546ff34a57faaefd41fce323c691902501c5 (diff) | |
download | libdrm-926c80568691e04abdfcd21b6e9be61331e95b03.tar.gz libdrm-926c80568691e04abdfcd21b6e9be61331e95b03.tar.bz2 libdrm-926c80568691e04abdfcd21b6e9be61331e95b03.zip |
amdgpu : move management of user fence from libdrm to UMD
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Diffstat (limited to 'amdgpu/amdgpu.h')
-rw-r--r-- | amdgpu/amdgpu.h | 39 |
1 files changed, 30 insertions, 9 deletions
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index 76319687..125377c2 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -311,6 +311,20 @@ struct amdgpu_cs_ib_info { }; /** + * Structure describing fence information + * + * \sa amdgpu_cs_request, amdgpu_cs_query_fence, + * amdgpu_cs_submit(), amdgpu_cs_query_fence_status() +*/ +struct amdgpu_cs_fence_info { + /** buffer object for the fence */ + amdgpu_bo_handle handle; + + /** fence offset in the unit of sizeof(uint64_t) */ + uint64_t offset; +}; + +/** * Structure describing submission request * * \note We could have several IBs as packet. e.g. CE, CE, DE case for gfx @@ -357,6 +371,16 @@ struct amdgpu_cs_request { * IBs to submit. Those IBs will be submit together as single entity */ struct amdgpu_cs_ib_info *ibs; + + /** + * The returned sequence number for the command submission + */ + uint64_t seq_no; + + /** + * The fence information + */ + struct amdgpu_cs_fence_info fence_info; }; /** @@ -841,22 +865,20 @@ int amdgpu_cs_query_reset_state(amdgpu_context_handle context, * from the same GPU context to the same ip:ip_instance:ring will be executed in * order. * + * The caller can specify the user fence buffer/location with the fence_info in the + * cs_request.The sequence number is returned via the 'seq_no' paramter + * in ibs_request structure. + * * * \param dev - \c [in] Device handle. * See #amdgpu_device_initialize() * \param context - \c [in] GPU Context * \param flags - \c [in] Global submission flags - * \param ibs_request - \c [in] Pointer to submission requests. + * \param ibs_request - \c [in/out] Pointer to submission requests. * We could submit to the several * engines/rings simulteniously as * 'atomic' operation * \param number_of_requests - \c [in] Number of submission requests - * \param fences - \c [out] Pointer to array of data to get - * fences to identify submission - * requests. Timestamps are valid - * in this GPU context and could be used - * to identify/detect completion of - * submission request * * \return 0 on success\n * <0 - Negative POSIX Error code @@ -873,8 +895,7 @@ int amdgpu_cs_query_reset_state(amdgpu_context_handle context, int amdgpu_cs_submit(amdgpu_context_handle context, uint64_t flags, struct amdgpu_cs_request *ibs_request, - uint32_t number_of_requests, - uint64_t *fences); + uint32_t number_of_requests); /** * Query status of Command Buffer Submission |