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path: root/src/jit/lsraxarch.cpp
AgeCommit message (Expand)AuthorFilesLines
2018-04-09Handle last uses that become containedCarol Eidt1-1/+15
2018-03-22Implement SetAllVector256Fei Peng1-0/+14
2018-03-15Merge pull request #16813 from CarolEidt/FixDD544983Carol Eidt1-1/+6
2018-03-14Mark operands of dead FIELD_LIST as unusedCarol Eidt1-1/+6
2018-03-10Adding support for the Extend, GetLowerHalf, and StaticCast AVX intrinsicsTanner Gooding1-0/+5
2018-03-09Fix the RMW delay handling for hwintrinsic nodes with RMW semantics and more ...Tanner Gooding1-0/+13
2018-03-08Updating isRMWRegOper, OperIsCommutative, and canBeContained to handle HWIntr...Tanner Gooding1-24/+5
2018-03-05Implement LoadHigh, LoadLow, and SetScalarVector128 SSE2 HW intrinsicsJacek Blaszczynski1-1/+2
2018-03-05Merge pull request #16727 from CarolEidt/NoIndirByteCarol Eidt1-1/+3
2018-03-02Don't force byte regs for indir addressCarol Eidt1-1/+3
2018-03-02Implement Shuffle* SSE2 hardware intrinsicsJacek Blaszczynski1-4/+2
2018-03-02Merge pull request #16646 from fiigii/insertextractCarol Eidt1-0/+14
2018-03-01Implement SSE4.1 insert and extractFei Peng1-0/+14
2018-02-28Implementing the SSE2 MaskMove intrinsicTanner Gooding1-0/+8
2018-02-28Set isInternalRegDelayFree for several of the x86 hwintrinsicsTanner Gooding1-0/+2
2018-02-28Adding some asserts that we won't overwrite one of the hwintrinsic operand re...Tanner Gooding1-6/+35
2018-02-28Adding partial support for the SSE41 hardware intrinsicsTanner Gooding1-0/+7
2018-02-26Update the table-driven framework to support x86 imm-intrinsics.Fei Peng1-20/+22
2018-02-21Adding support for the SSE3 and SSSE3 hardware intrinsicsTanner Gooding1-0/+1
2018-02-16Don't set delayRegFree if no targetCarol Eidt1-2/+3
2018-02-13Implement scalar Sse2 hardware intrinsicsJacek Blaszczynski1-0/+5
2018-02-02Update CoreClr, CoreFx to preview2-26202-06, preview2-26202-01, respectively ...dotnet-maestro-bot1-1/+1
2018-02-01Merge pull request #16092 from CarolEidt/RefactorRefBuildingCarol Eidt1-419/+85
2018-02-01Refactor RefPosition and Interval BuildingCarol Eidt1-419/+85
2018-02-01Fixing some of the x86 HWIntrinsics to only use byteable registers, where req...Tanner Gooding1-1/+1
2018-01-31Delete GenTreePtr. (#16027)Sergey Andreenko1-27/+27
2018-01-25Merge pull request #16005 from CarolEidt/Fix15848Carol Eidt1-2/+0
2018-01-24Disable the ConvertToUInt intrinsics by removing them from simdintrinsiclist.hCarol Eidt1-2/+0
2018-01-24Delete Ptr typedefs from jit src. (#15983)Sergey Andreenko1-1/+1
2018-01-19Fix desktop buildBruce Forstall1-2/+2
2018-01-19Merge pull request #15930 from mikedn/useless-codeCarol Eidt1-10/+0
2018-01-19Remove some redundant code from TreeNodeInfoInitMike Danes1-10/+0
2018-01-19Merge SSE intrinsics into the table-driven frameworkFei Peng1-3/+0
2018-01-18table drive Intel hardware intrinsicFei Peng1-9/+17
2018-01-16Adding support for the SSE Set scalar intrinsicTanner Gooding1-0/+6
2018-01-16Adding support for the SSE Compare<op>Ordered and Compare<op>Unordered scalar...Tanner Gooding1-0/+8
2018-01-16Adding support for the SSE ConvertTo Int32, Int32WithTruncation, Int64WithTru...Tanner Gooding1-2/+1
2018-01-16Adding support for the SSE StaticCast intrinsicTanner Gooding1-0/+8
2018-01-16Adding support for the SSE Shuffle intrinsicTanner Gooding1-0/+21
2018-01-16Adding support for the SSE Set, SetAll, and SetZero intrinsicsTanner Gooding1-14/+46
2018-01-14Adding SSE4.1 intrinsic support for Round, Ceiling, and Floor.Tanner Gooding1-2/+9
2018-01-10Fix ARM GCStress hole with byref write barrier helperBruce Forstall1-10/+1
2017-12-18Eliminate gtLsraInfo from GenTreeCarol Eidt1-440/+450
2017-11-20Set reg conflicts on contained INDCarol Eidt1-2/+30
2017-11-14Change VEX-encoding selection to avoid AVX-SSE transition penaltiesFei Peng1-7/+10
2017-10-31Limit byte register candidates for CRC32Fei Peng1-0/+15
2017-10-30Merge pull request #14456 from fiigii/crc32Carol Eidt1-0/+27
2017-10-27Merge pull request #14678 from fiigii/vexCarol Eidt1-13/+11
2017-10-25Enable Crc32 , Popcnt, Lzcnt intrinsicsFei Peng1-0/+27
2017-10-25Decoupling SIMD levels from instruction setsFei Peng1-13/+11