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2020-03-25[JIT/x86] Fix LinearScan::allocateRegisters (#26649)Konstantin Baladurin1-1/+1
Check for `lvLRACandidate` instead of `!lvDoNotEnregister` when checking whether `this` may be enregistered and has an Interval.
2020-03-25Linux/x86: fix build (#26594)Konstantin Baladurin1-0/+2
2019-06-27Don't reload or spill for keepAliveThis (#25441)Carol Eidt1-0/+2
Fix #25433
2019-05-22Fix x86 synchronized method (#24703)Carol Eidt1-1/+48
For the JIT32_GCENCODER the this pointer must be either kept in a single register or on the stack. Fix #24166
2019-05-07Merge pull request #23587 from BrianBohe/brbohe/moving_variableLiveRangeSergey Andreenko1-1/+1
Moving VariableLiveRanges classes outside Compiler class
2019-04-22Fix Arm64 UpperVector save/restore (#24043)Carol Eidt1-64/+103
* Fix Arm64 UpperVector save/restore Change the general handling of end-of-block restores so that we always have a RefPosition on which to allocate the register needed on Arm64. Fix #23885
2019-04-16Arm64 vector ABI (#23675)Carol Eidt1-1/+1
* Support for Arm64 Vector ABI Extend HFA support to support vectors as well as floating point types. This requires that the JIT recognize vector types even during crossgen, so that the ABI is supported consistently. Also, fix and re-enable the disabled Arm64 Simd tests. Fix #16022
2019-04-15Fix lsraBlockEpoch check.Sergey Andreenko1-7/+17
2019-04-12Don't Free UpperVector (#23889)Carol Eidt1-21/+26
* Don't Free UpperVector UpperVector regs are freed at their time of use, and shouldn't be freed when the last RefPosition is encountered. Also, we need to specify all 3 operands for vinsertf128 Fix #23861 Fix #23904 Fix #23804
2019-04-04Improve Upper Vector Save/Restore (#23344)Carol Eidt1-96/+311
Improve Upper Vector Save/Restore In order to avoid saving and restore the upper half of large vectors around every call even if they are not used, separately model the upper half of large vector lclVars, and track whether the large vector lclVar is partially-spilled, in which case its upper half resides in its upper half Interval's location. Fix #18144
2019-04-01LSRA cleanup (#23617)Carol Eidt1-60/+100
* LSRA cleanup These are zero-diff changes. Some cleanup, some in preparation for improvemetns to save/restore of upper vectors.
2019-03-29Moving VariableLiveRanges classes outside Compiler classBrian Bohe1-1/+1
Signed-off-by: Brian Bohe <brianbohe@gmail.com>
2019-03-29A new way of tracking variables (#23373)Brian Bohe1-0/+9
* Defining VariableLiveRange class * Adding some typedefs to avoid rewriting * Defining VariableLiveDescriptor class * Initializing VariableLiveRange structures before BasicBlock code is being generated * Getting a siVarLoc for variable homes from a given LclVarDsc and stack level * Defining VariableLiveKeeper class * Reporting VariableLiveRanges on changes of variable livenesss or variable homes * Adding USING_VARIABLE_LIVE_RANGE flag to enable disable VariableLiveRange * Send VariableLiveRanges to debugger * Reporting variable homes on prolog * Wrong argument * Miss to change variable homes count before sending them to debugger * Adding dumper of VariableLiveRanges for each blocks and end of code generation * Close all open VaribleLiveRanges on last BasicBlock * Changing order of properties initialization on VariableLiveRange constructor * Type error on assignation * Rephrasing comments, moving dumps and fixing typos * Changing const VARSET_TP* for VARSET_VALARG_TP on args * Variable home was variable location in VariableLiveRange context * Rephrase and rename of VariableLiveKeeper properties * Missing some renames * Adding const where BasicBlock should not be modified * siBeginBlock and siInit have support for debug code for VariableLiveRange and siScope info * Adding USING_VARIABLE_LIVE_RANGE flags on methods definition. * Variable home -> variable location * Renaming and rephrasing names and uses of VariableLiveRange * Moving LiveRangeDumper ctor to class declation * Removing destructors Signed-off-by: Brian Bohe <brianbohe@gmail.com> * Removing blank spaces and reordering functions inside class definition Signed-off-by: Brian Bohe <brianbohe@gmail.com> * Miss to increment the index after refactoring * Logic for keeping the last BasicBlock end IL offset is shared between siScope and VariableLiverange for debug code * Missing to print on debug the last block VariableLiveRanges * Avoid updating VariableLiveRange when unspilling and dying at the same assembly instruction * Rephrasing #ifs and #ifdefs * Calling VariableLiveKeeper in one line * Avoid copying siVarLoc on genSetScopeInfo * Removing unused args from eeSetLVinfo * Changing VariableLiveKeeper ctor * Typo Signed-off-by: Brian Bohe <brianbohe@gmail.com> * Updating VariableLiveDescriptor ctor Signed-off-by: Brian Bohe <brianbohe@gmail.com> * Error on first argument Signed-off-by: Brian Bohe <brianbohe@gmail.com> * Changing reference for pointer Signed-off-by: Brian Bohe <brianbohe@gmail.com> * Renaming assembly offset -> native offset * removing unnecesary comments and asserts Signed-off-by: Brian Bohe <brianbohe@gmail.com> * Update VariableLiveRange dump message Signed-off-by: Brian Bohe <brianbohe@gmail.com> * Moving VariableLiveRanges classes inside VariableLiveKeeper * Wrong flag name * Adding documentation about how we track variables for debug info Signed-off-by: Brian Bohe <brianbohe@gmail.com> * Adding opened issues to doc file Signed-off-by: Brian Bohe <brianbohe@gmail.com> * Changing dump tittle Signed-off-by: Brian Bohe <brianbohe@gmail.com> * Renaming VariableLiveKeeper property Signed-off-by: Brian Bohe <brianbohe@gmail.com> * Update documentation Signed-off-by: Brian Bohe <brianbohe@gmail.com> * Updating comments on flags Signed-off-by: Brian Bohe <brianbohe@gmail.com> * Setting Scope Info as default way of tracking variables for debug info Signed-off-by: Brian Bohe <brianbohe@gmail.com>
2019-02-02Spill tree temp large vectors around calls (#22311)Carol Eidt1-11/+52
* Spill tree temp large vectors around calls The code was there to handle lclVars, but there was an implicit assumption that non-lclVar large vector tree temps would never be live across a call. Fixes the GitHub_20657 failure in #22253
2019-02-02Propagate preferences (#19429)Carol Eidt1-65/+93
* Propagate preferences Instead of selecting a single relatedInterval for preferencing, follow the chain of relatedIntervals (preferenced intervals). Change when preferences are propagated to the relatedInterval; do it in allocateRegisters, so that we can update it when we see a last use. Also tune when and how intervals are preferenced, including allowing multiple uses on an RMW node to have the target as their preference. Fixes #11463 Contributes to #16359
2018-10-31Arm32: Handle live-out double reg in resolutionCarol Eidt1-4/+9
When handling critical edges, live-in and live-out reg masks must contain both halves of double regs.
2018-10-30Fix `JitStressRegs=0x1` issue with `RefTypeUpperVectorSaveDef`. (#20623)Sergey Andreenko1-0/+1
* Add a repro test. * Fix the issue. * Add comments
2018-10-17Delete `FixupIfSIMDLocal`. (#20360)Sergey Andreenko1-3/+3
* Fix the strange `ifdef ` placement. * Fix comments/refactoring of `LinearScan::BuildReturn`. * Delete `FixupIfSIMDLocal`. Do not change `LCL_FLD(long)` back to `LCL_VAR(simd8)`,
2018-09-20Handle partial multireg COPYCarol Eidt1-0/+10
A multireg COPY will only have a valid register for indices that require copying. Thus, the `GetRegCount` method must return the highest index that has a valid register. Fix #20063
2018-08-28Handle multiReg COPYCarol Eidt1-22/+33
On x86, `MUL_LONG` wasn't considered a multi-reg node, as it should be, so that when it gets spilled or copied, the additional register will be correctly handled. Also, the ARM and X86 versions of genStoreLongLclVar should be identical and shared (neither version were handling the copy of a `MUL_LONG`). Finally, fix the LSRA dumping of multi-reg nodes. Fix #19397
2018-08-25Remove some GT_ASG_op leftovers (#18205)mikedn1-1/+1
2018-08-22define FMT_BB as "BB%02u" and use it uniformly in the codebaseBrian Sullivan1-15/+15
We use the following format when print the BasicBlock number: bbNum This define is used with string concatenation to put this in printf format strings
2018-08-21Cleanup unnecessary casts in roundUpEgor Chesakov1-1/+1
2018-07-19Merge pull request #18999 from CarolEidt/Fix16359Carol Eidt1-9/+2
Arm64: Fix handling of IP0 & IP1
2018-07-18JIT: force all local var ref counts to be accessed via API (#18979)Andy Ayers1-12/+12
This is a preparatory change for auditing and controlling how local variable ref counts are observed and manipulated. See #18969 for context. No diffs seen locally. No TP impact expected. There is a small chance we may see some asserts in broader testing as there were places in original code where local ref counts were incremented without checking for possible overflows. The new APIs will assert for overflow cases.
2018-07-18Arm64: Fix handling of IP0 & IP1Carol Eidt1-9/+2
These are sometimes mandated to be allocated to certain nodes, but they were not in the list of allocatable registers (REG_VAR_ORDER). This led to special handling in LSRA, which, it turns out, was incomplete. This resulted in failures for JitStressRegs=0x200. Based on the discussion in #14607, this adds IP0 to RBM_CALLEE_TRASH_NOGC, and fixes the REG_VAR_ORDER. Fix #14607, Fix #16359, Fix #17861
2018-07-16Ensure BuildUse uses the correct reg numberCarol Eidt1-1/+1
`BuildUse` was setting the regNumber for all of the uses of a multi-reg node to the main/first regNum. This was missed because this results in a def/use conflict on that reg (the def was set correctly), which is generally resolved in favor of the def. The exception is when there is a kill of the register in between, in which case the use tries to allocate the register its been assigned, causing the `farthestRefPhysRegRecord != nullptr` assert (aka "a register can't be found to spill"). This fixes the specific issue, and adds additional asserts to identify future/additional such issues. The new asserts depend upon all the regNums being appropriately when/if any are set, which wasn't always the case prior to register allocation. Fix #18153
2018-07-10Merge pull request #18805 from CarolEidt/Fix18746Carol Eidt1-0/+2
Don't change PUTARG_REG spill type on arm64
2018-07-06Don't change PUTARG_REG type on arm64Carol Eidt1-0/+2
Fix #18746
2018-07-03Merge pull request #18504 from mikedn/comp-smallBruce Forstall1-4/+4
Make Compiler and CodeGen objects smaller
2018-07-03Remove Interval::isMultiRegCarol Eidt1-18/+1
This is no longer used after #16517
2018-06-30Move temp info from Compiler to RegSetMike Danes1-4/+4
Temporaries are only used during register allocation and code generation. They waste space (136 bytes) in the compiler object during inlining.
2018-06-30Pass CompAllocator by value (#15025)mikedn1-5/+2
Passing CompAllocator objects by value is advantageous because it no longer needs to be dynamically allocated and cached. CompAllocator instances can now be freely created, copied and stored, which makes adding new CompMemKind values easier. Together with other cleanup this also improves memory allocation performance by removing some extra levels of indirection that were previously required - jitstd::allocator had a pointer to CompAllocator, CompAllocator had a pointer to Compiler and Compiler finally had a pointer to ArenaAllocator. Without MEASURE_MEM_ALLOC enabled, both jitstd::allocator and CompAllocator now just contain a pointer to ArenaAllocator. When MEASURE_MEM_ALLOC is enabled CompAllocator also contains a pointer but to a MemStatsAllocator object that holds the relevant memory kind. This way CompAllocator is always pointer sized so that enabling MEASURE_MEM_ALLOC does not result in increased memory usage due to objects that store a CompAllocator instance. In order to implement this, 2 additional signficant changes have been made: * MemStats has been moved to ArenaAllocator, it's after all the allocator's job to maintain statistics. This also fixes some issues related to memory statistics, such as not tracking the memory allocated by the inlinee compiler (since that one used its own MemStats instance). * Extract the arena page pooling logic out of the allocator. It doesn't make sense to pool an allocator, it has very little state that can actually be reused and everyting else (including MemStats) needs to be reset on reuse. What really needs to be pooled is just a page of memory. Since this was touching allocation code the opportunity has been used to perform additional cleanup: * Remove unnecessary LSRA ListElementAllocator * Remove compGetMem and compGetMemArray * Make CompAllocator and HostAllocator more like the std allocator * Update HashTable to use CompAllocator * Update ArrayStack to use CompAllocator * Move CompAllocator & friends to alloc.h
2018-06-29Corrected a few typos in the documentation and comments (#18706)Phil Garcia1-6/+6
* Corrected a few typos in the documentation and comments * Corrected a few typos in the documentation and comments * Corrected a few typos in the documentation and comments * Corrected a few typos in the documentation and comments * Corrected a few typos in the documentation and comments * Corrected a few typos in the documentation and comments
2018-06-28LSRA: fix multi-reg ops under FIELD_LISTCarol Eidt1-0/+4
Need to build a use for each reg. Also, dump the defList if it's not empty at end of block.
2018-06-14[Windows|Arm64|Vararg] Add FEATURE_ARG_SPLIT (#18346)Jarret Shook1-6/+10
* [ARM64|Windows|Vararg] Add FEATURE_ARG_SPLIT Enable splitting >8 byte <= 16 byte structs for arm64 varargs between x7 and virtual stack slot 0. * Force notHfa for vararg methods * Correctly pass isVararg * Correct var name
2018-06-13Fix enregistered lclFld bug (#18418)Carol Eidt1-115/+98
* Fix enregistered lclFld bug In `impFixupStructReturnType()`, don't transform to `GT_LCL_FLD` if we have a scalar lclVar. Also, to avoid future bad codegen, add verification and recovery code to Lowering. Fix #18408 * Extract the full conditions for whether a lclVar is a reg candidate, so it can be called from the assert in Lowering. * Review feedback
2018-05-24Typo (#18122)John Doe1-2/+2
* acquringing -> acquiring * Activ -> Active * activley -> actively * acutal -> actual * bIncomingIPAdddefed -> bIncomingIPAddRefed * adddr -> addr * readding -> reading * Addfunction -> AddFunction * additionnal -> additional * Additonal -> Additional * Additonally -> Additionally * Addresss -> Address * addtion -> addition * aded -> added * aditional -> additional * adjustements -> adjustments * Adress -> Address * afer -> after * aformentioned -> aforementioned * afte -> after * agains -> against * agaisnt -> against * aggresively -> aggressively * aggreates -> aggregates * aggregious -> egregious * aginst -> against * agregates -> aggregates * Agressive -> Aggressive * ahve -> have * ajdust -> adjust * ajust -> adjust * alement -> element * algoritm -> algorithm * alighnment -> alignment * alignmant -> alignment * constraits -> constraints * Allcator -> Allocator * alllocate -> allocate * alloacted -> allocated * allocatate -> allocate * allocatoror -> allocator * alloctaed -> allocated * alloction -> allocation * alloted -> allotted * allt he -> all the * alltogether -> altogether * alocate -> allocate * alocated -> allocated * Alocates -> Allocates * alogrithm -> algorithm * aloocate -> allocate * alot -> a lot * alwasy -> always * alwyas -> always * alwys -> always
2018-05-23Create RefPositions without TreeNodeInfo (#16517)Carol Eidt1-199/+59
* Create RefPositions without TreeNodeInfo * Remove all references to TreeNodeInfo * Fix function header comments
2018-05-22Remove JIT LEGACY_BACKEND code (#18064)Bruce Forstall1-6/+1
Remove JIT LEGACY_BACKEND code All code related to the LEGACY_BACKEND JIT is removed. This includes all code related to x87 floating-point code generation. Almost 50,000 lines of code have been removed. Remove legacyjit/legacynonjit directories Remove reg pairs Remove tiny instruction descriptors Remove compCanUseSSE2 (it's always true) Remove unused FEATURE_FP_REGALLOC
2018-03-30Tighten arm32/arm64 write barrier kill reg setsBruce Forstall1-3/+3
The JIT write barrier helpers have a custom calling convention that avoids killing most registers. The JIT was not taking advantage of this, and thus was killing unnecessary registers when a write barrier was necessary. In particular, some integer callee-trash registers are unaffected by the write barriers, and no floating-point register is affected. Also, I got rid of the `FEATURE_WRITE_BARRIER` define, which is always set. I also put some code under `LEGACY_BACKEND` for easier cleanup later. I removed some unused defines in target.h for some platforms.
2018-03-28Merge pull request #17126 from CarolEidt/Fix545500Carol Eidt1-3/+44
ARM: Fix reg resolution for doubles
2018-03-27Fix commentCarol Eidt1-1/+3
2018-03-26Fix conditionCarol Eidt1-2/+16
2018-03-23Merge pull request #17072 from CarolEidt/Fix545505Carol Eidt1-17/+36
ARM: call compRsvdRegCheck later
2018-03-22ARM: correctly unassign constant doubleCarol Eidt1-4/+2
When a `RefTypeFixedReg` is encountered for a floating point register, if it is currently holding a double constant, we need to free both halves - but the current register be either half.
2018-03-22ARM: Fix reg resolution for doublesCarol Eidt1-3/+28
1) When an odd float register becomes free, we may need to add the corresponding (even) double register to `targetRegsReady` (this was the bug) 2) When an even float register becomes free, we can't add it to `targetRegsReady` unless it's other half is also free.
2018-03-21Fix release buildCarol Eidt1-1/+1
2018-03-21Remove REG_OPT_RSVD from LSRA's candidate masks if it's reserved.Carol Eidt1-16/+24
2018-03-20ARM: call compRsvdRegCheck laterCarol Eidt1-1/+12
For RyuJIT backend, the number of locals can change due to decomposition and lowering. So, determine whether to reserve a register for accessing large state displacements just prior to register allocation. This requires ensuring that the stack offset for promoted longs is fixed up, as for promoted reg structs on ARM64. This is all a bit more difficult on LEGACY_BACKEND because the register allocator can change its mind about whether or not it's going to have a frame, so that is left as before.
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