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path: root/src/jit/lowerxarch.cpp
AgeCommit message (Expand)AuthorFilesLines
2017-02-02Refactor TreeNodeInfoInitCarol Eidt1-3349/+11
2017-01-26Stop address mode building in TreeNodeInfoInit passBruce Forstall1-78/+1
2017-01-17Move small unsigned type tweak to LowerCompareMike Danes1-10/+0
2017-01-17Introduce OperIsMike Danes1-4/+4
2017-01-17Handle cmp(and(x, y), 0)Mike Danes1-0/+3
2017-01-17Contain "op1" from "cmp op1, icon" only if types are identicalMike Danes1-1/+1
2017-01-17Remove unused codeMike Danes1-47/+36
2017-01-17Move and-cmp-test transform from TreeNodeInfoInitCmp to LowerCompareMike Danes1-117/+1
2017-01-17Add GT_TEST_EQ and GT_TEST_NEMike Danes1-0/+2
2017-01-17Move and-cmp-nonzero transform from TreeNodeInfoInitCmp to LowerCompareMike Danes1-14/+0
2017-01-17Move cast elision from TreeNodeInfoInitCmp to LowerCompareMike Danes1-86/+0
2017-01-17Move narrowing from TreeNodeInfoInitCmp to LowerCompareMike Danes1-57/+0
2017-01-11Merge pull request #8588 from litian2025/AVX_SSESivarv1-1/+33
2017-01-10fix format errorLi Tian1-1/+1
2017-01-10fix comments, assertion failure in crossgen mscorlibLi Tian1-2/+2
2017-01-10rename, use getSIMDInstructionSet()Li Tian1-9/+9
2017-01-10fix format errorLi Tian1-2/+3
2017-01-10Fix handling of PutArgStkCarol Eidt1-43/+28
2017-01-10remove unnecessary check in CalleeSavedFltRegsLi Tian1-6/+5
2017-01-08Remove AVX/SSE transition penaltiesLi Tian1-1/+33
2016-12-21Use Pabsd/pabsw/pabsb instructions for Abs SIMD intrinsic on SSE4 and above t...sivarv1-3/+8
2016-12-20Fix GT_LOCKADD register specification.sivarv1-1/+26
2016-12-13Fix incorrect compare narrowing in TreeNodeInfoInitCmpMike Danes1-27/+26
2016-12-08Remove an unused local variableHyung-Kyu Choi1-1/+0
2016-12-05Merge pull request #8461 from sivarv/shiftFixSivarv1-6/+10
2016-12-05Compare opt against zero involving a shift oper.sivarv1-6/+10
2016-12-02RyuJIT/x86: Implement TYP_SIMD12 supportBruce Forstall1-0/+13
2016-11-28Enable using SSE3_4 instruction set for SIMD codegen.sivarv1-16/+13
2016-11-23Merge pull request #7847 from CarolEidt/Fix278375Carol Eidt1-12/+77
2016-11-23Change vector equality to use pmovmskbMike Danes1-3/+3
2016-11-22x86: not all fields of promoted struct need regsCarol Eidt1-12/+77
2016-11-21Merge pull request #8106 from mikedn/magic-divRussell C Hadley1-4/+9
2016-11-18Reinstate the struct optimization changes:Carol Eidt1-2/+16
2016-11-18Fix codegen for `(umod (gt_long) (const int))`.Pat Gavlin1-0/+4
2016-11-15Fix GT_MULHI register requirementsMike Danes1-4/+9
2016-11-03Revert "Enable optimization of structs"Jan Kotas1-16/+2
2016-11-01Rotate Left/Right xarch instructions don't set ZF and ZF flag.sivarv1-2/+6
2016-11-01Merge pull request #7677 from CarolEidt/StructOptsCarol Eidt1-2/+16
2016-10-26Optimize 'test' instruction for op1 == 0 and op1 != 0 where op1 is known to s...sivarv1-1/+47
2016-10-21Optimize Vector<int>.Dot on AVX.sivarv1-10/+31
2016-10-20Enable optimization of structsCarol Eidt1-2/+16
2016-10-12Fix assertion regarding byteable xor reg,reg when ngen'ing desktop mscorlibBruce Forstall1-24/+52
2016-10-10Merge pull request #7518 from adiaaida/cmpByteableMichelle McDaniel1-14/+67
2016-10-10Force byteable register for CMP if op2 is CNS_INTMichelle McDaniel1-14/+67
2016-10-10Address PR feedback.Pat Gavlin1-22/+23
2016-10-09Fix the codegen for by-value struct args on x86.Pat Gavlin1-30/+123
2016-10-07Force byteable registers for indir op sourceMichelle McDaniel1-0/+14
2016-09-29Merge pull request #7407 from sivarv/simdOptSivarv1-2/+75
2016-09-29Optimize codegen when SIMD (in)Equality that produces bool result is compared...sivarv1-2/+75
2016-09-28Fix lowering's containment analysis.Pat Gavlin1-32/+151
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