index
:
platform/upstream/coreclr
accepted/tizen_4.0_base
accepted/tizen_4.0_unified
accepted/tizen_5.0_base
accepted/tizen_5.5_unified
accepted/tizen_5.5_unified_mobile_hotfix
accepted/tizen_5.5_unified_wearable_hotfix
accepted/tizen_6.0_unified
accepted/tizen_6.0_unified_hotfix
accepted/tizen_6.5_unified
accepted/tizen_base
accepted/tizen_common
accepted/tizen_ivi
accepted/tizen_mobile
accepted/tizen_tv
accepted/tizen_unified
asoldatov
backup/release/2.0.0_tizen/20170828
backup/release/2.0.0_tizen/20170906
backup/tizen_5.5/20190304
backup/tizen_base_2.0.0
backup/tizen_base_2.1.1-upd2
master
origin/backup/release/2.0.0_tizen_4.0/20170908
sandbox/adrob/asan
sandbox/adrob/asan.old
sandbox/akazmin/asan_annotate_buff
sandbox/ches01/asan
sandbox/ches01/asan_ARM
sandbox/ches01/asan_ARM_v2
sandbox/ches01/asan_amd64
sandbox/ches01/asan_amd64_intel_syntax
sandbox/ches01/asan_amd64_v2
sandbox/ches01/integrate-libasansi
sandbox/ches01/integrate-libasansi_debug
sandbox/ches01/integrate-libasansi_debug_v2
sandbox/denis13/gcc6x
sandbox/dkson95/clang
sandbox/dkson95/gcc_6_2_1
sandbox/dkson95/hardfp
sandbox/dkson95/hardfp_rebase
sandbox/dkson95/integrate-libasansi
sandbox/dkson95/tizen
sandbox/giuliana/fix_llvm_path
sandbox/giuliana/gcc_6_2_1
sandbox/giuliana/x86_baselibs
sandbox/jaehun77/hardfp
sandbox/mkashkarov/debug_build
sandbox/mkashkarov/test
sandbox/mkashkarov/tizen_6.0_build
sandbox/nmerinov/llvm
sandbox/vbarinov/clean-clang
sandbox/wangbiao/rpm_upgrade
tc
tizen
tizen_4.0
tizen_4.0_base
tizen_4.0_tv
tizen_5.0_base
tizen_5.5
tizen_5.5_mobile_hotfix
tizen_5.5_tv
tizen_5.5_wearable_hotfix
tizen_6.0
tizen_6.0_hotfix
tizen_6.5
tizen_base
Domain: Dotnet / Core; Licenses: MIT;
Alexander Soldatov <soldatov.a@samsung.com>, Dmitri Botcharnikov <dmitry.b@samsung.com>, Igor Kulaychuk <i.kulaychuk@samsung.com>
summary
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author
committer
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path:
root
/
src
/
jit
/
emitxarch.h
Age
Commit message (
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)
Author
Files
Lines
2017-03-06
Un-clang-format-horrible-ify emitIns_Call() and genEmitCall()
Bruce Forstall
1
-21
/
+27
2017-02-23
Rewrite Is4ByteAVXInstruction() and Is4ByteSSE4Instruction()
Fei Peng
1
-0
/
+1
2017-02-05
Enable SIMD for RyuJIT/x86
Bruce Forstall
1
-1
/
+11
2017-01-10
fix comments, assertion failure in crossgen mscorlib
Li Tian
1
-2
/
+2
2017-01-08
Remove AVX/SSE transition penalties
Li Tian
1
-0
/
+28
2016-11-30
Fix x86 encoder to use 64-bit type to accumulate opcode/prefix bits
Bruce Forstall
1
-36
/
+52
2016-11-29
Merge pull request #8291 from sivarv/sse34
Sivarv
1
-0
/
+18
2016-11-28
Enable using SSE3_4 instruction set for SIMD codegen.
sivarv
1
-0
/
+18
2016-11-28
Factor out common stack adjustment code
Bruce Forstall
1
-0
/
+12
2016-08-11
Reformat jit sources with clang-tidy and format
Michelle McDaniel
1
-449
/
+349
2016-07-29
Massage code for clang-format
Michelle McDaniel
1
-1
/
+1
2016-07-26
Enable multireg returns on Arm64
Brian Sullivan
1
-4
/
+4
2016-04-22
Fix #3561: assert on RyuJIT x86 when generating shl by 1
Bruce Forstall
1
-2
/
+2
2016-02-29
Add support for emitting GC-ness of the second return register for 16 byte
Lubomir Litchev
1
-40
/
+44
2016-01-27
Update license headers
dotnet-bot
1
-4
/
+3
2015-12-11
Port of all JIT changes for .NET Framework 4.6.1 changes
Brian Sullivan
1
-2
/
+0
2015-01-30
Initial commit to populate CoreCLR repo
dotnet-bot
1
-0
/
+536