diff options
| author | Andrew Au <andrewau@microsoft.com> | 2018-08-13 14:53:10 -0700 |
|---|---|---|
| committer | Andrew Au <cshung@gmail.com> | 2018-11-06 18:34:47 -0800 |
| commit | 7e94efe87f48b990e77e87f6f643cdf1ab51f951 (patch) | |
| tree | a09645b3853996d6c5df57dc547f98effa4796ac /src/pal | |
| parent | d5bb5d5b48feba48dbfe561c093a2b38e6f0e99d (diff) | |
| download | coreclr-7e94efe87f48b990e77e87f6f643cdf1ab51f951.tar.gz coreclr-7e94efe87f48b990e77e87f6f643cdf1ab51f951.tar.bz2 coreclr-7e94efe87f48b990e77e87f6f643cdf1ab51f951.zip | |
Fix ARM compilation issue
Diffstat (limited to 'src/pal')
| -rw-r--r-- | src/pal/prebuilt/inc/cordebug.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/pal/prebuilt/inc/cordebug.h b/src/pal/prebuilt/inc/cordebug.h index 59375ba4ce..f633fda7b1 100644 --- a/src/pal/prebuilt/inc/cordebug.h +++ b/src/pal/prebuilt/inc/cordebug.h @@ -8851,6 +8851,38 @@ enum CorDebugRegister REGISTER_ARM_R11 = ( REGISTER_ARM_R10 + 1 ) , REGISTER_ARM_R12 = ( REGISTER_ARM_R11 + 1 ) , REGISTER_ARM_LR = ( REGISTER_ARM_R12 + 1 ) , + REGISTER_ARM_D0 = ( REGISTER_ARM_LR + 1 ) , + REGISTER_ARM_D1 = ( REGISTER_ARM_D0 + 1 ) , + REGISTER_ARM_D2 = ( REGISTER_ARM_D1 + 1 ) , + REGISTER_ARM_D3 = ( REGISTER_ARM_D2 + 1 ) , + REGISTER_ARM_D4 = ( REGISTER_ARM_D3 + 1 ) , + REGISTER_ARM_D5 = ( REGISTER_ARM_D4 + 1 ) , + REGISTER_ARM_D6 = ( REGISTER_ARM_D5 + 1 ) , + REGISTER_ARM_D7 = ( REGISTER_ARM_D6 + 1 ) , + REGISTER_ARM_D8 = ( REGISTER_ARM_D7 + 1 ) , + REGISTER_ARM_D9 = ( REGISTER_ARM_D8 + 1 ) , + REGISTER_ARM_D10 = ( REGISTER_ARM_D9 + 1 ) , + REGISTER_ARM_D11 = ( REGISTER_ARM_D10 + 1 ) , + REGISTER_ARM_D12 = ( REGISTER_ARM_D11 + 1 ) , + REGISTER_ARM_D13 = ( REGISTER_ARM_D12 + 1 ) , + REGISTER_ARM_D14 = ( REGISTER_ARM_D13 + 1 ) , + REGISTER_ARM_D15 = ( REGISTER_ARM_D14 + 1 ) , + REGISTER_ARM_D16 = ( REGISTER_ARM_D15 + 1 ) , + REGISTER_ARM_D17 = ( REGISTER_ARM_D16 + 1 ) , + REGISTER_ARM_D18 = ( REGISTER_ARM_D17 + 1 ) , + REGISTER_ARM_D19 = ( REGISTER_ARM_D18 + 1 ) , + REGISTER_ARM_D20 = ( REGISTER_ARM_D19 + 1 ) , + REGISTER_ARM_D21 = ( REGISTER_ARM_D20 + 1 ) , + REGISTER_ARM_D22 = ( REGISTER_ARM_D21 + 1 ) , + REGISTER_ARM_D23 = ( REGISTER_ARM_D22 + 1 ) , + REGISTER_ARM_D24 = ( REGISTER_ARM_D23 + 1 ) , + REGISTER_ARM_D25 = ( REGISTER_ARM_D24 + 1 ) , + REGISTER_ARM_D26 = ( REGISTER_ARM_D25 + 1 ) , + REGISTER_ARM_D27 = ( REGISTER_ARM_D26 + 1 ) , + REGISTER_ARM_D28 = ( REGISTER_ARM_D27 + 1 ) , + REGISTER_ARM_D29 = ( REGISTER_ARM_D28 + 1 ) , + REGISTER_ARM_D30 = ( REGISTER_ARM_D29 + 1 ) , + REGISTER_ARM_D31 = ( REGISTER_ARM_D30 + 1 ) , REGISTER_ARM64_PC = 0, REGISTER_ARM64_SP = ( REGISTER_ARM64_PC + 1 ) , REGISTER_ARM64_FP = ( REGISTER_ARM64_SP + 1 ) , |