summaryrefslogtreecommitdiff
path: root/src/jit/lsra.cpp
diff options
context:
space:
mode:
authorsivarv <sivarv@microsoft.com>2016-11-08 18:08:31 -0800
committersivarv <sivarv@microsoft.com>2016-11-08 18:08:31 -0800
commit2eada9c3cf8a7f4af0cbcea68145e89b85b66d79 (patch)
tree5244a674e47c88b5d211a8863b24b20d20749b1b /src/jit/lsra.cpp
parenta194fe7037ea6db117e6f6e30d6533468ecee04d (diff)
downloadcoreclr-2eada9c3cf8a7f4af0cbcea68145e89b85b66d79.tar.gz
coreclr-2eada9c3cf8a7f4af0cbcea68145e89b85b66d79.tar.bz2
coreclr-2eada9c3cf8a7f4af0cbcea68145e89b85b66d79.zip
If the very first ref position of an interval has a register assignment of RBM_NONE indicate it could also be a regOptional
Diffstat (limited to 'src/jit/lsra.cpp')
-rw-r--r--src/jit/lsra.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/jit/lsra.cpp b/src/jit/lsra.cpp
index 3b22f1d8b6..b0ef498971 100644
--- a/src/jit/lsra.cpp
+++ b/src/jit/lsra.cpp
@@ -8576,8 +8576,8 @@ void LinearScan::resolveRegisters()
}
if (firstRefPosition->registerAssignment == RBM_NONE || firstRefPosition->spillAfter)
{
- // Either this RefPosition is spilled, or it is not a "real" def or use
- assert(firstRefPosition->spillAfter ||
+ // Either this RefPosition is spilled, or regOptional or it is not a "real" def or use
+ assert(firstRefPosition->spillAfter || firstRefPosition->AllocateIfProfitable() ||
(firstRefPosition->refType != RefTypeDef && firstRefPosition->refType != RefTypeUse));
varDsc->lvRegNum = REG_STK;
}