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| author | Carol Eidt <carol.eidt@microsoft.com> | 2018-07-19 11:08:33 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-07-19 11:08:33 -0700 |
| commit | f52752659c90c912af263b378d50e0dd0dcaf120 (patch) | |
| tree | b24d7285213adc61895d02b9a0f0fdd3750d2ab7 /src/jit/lsra.cpp | |
| parent | 04fb905d7168740b1787594b5e46a18639e931d3 (diff) | |
| parent | 6e7e087daeba074c93ee1825d38246a18e276f04 (diff) | |
| download | coreclr-f52752659c90c912af263b378d50e0dd0dcaf120.tar.gz coreclr-f52752659c90c912af263b378d50e0dd0dcaf120.tar.bz2 coreclr-f52752659c90c912af263b378d50e0dd0dcaf120.zip | |
Merge pull request #18999 from CarolEidt/Fix16359
Arm64: Fix handling of IP0 & IP1
Diffstat (limited to 'src/jit/lsra.cpp')
| -rw-r--r-- | src/jit/lsra.cpp | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/src/jit/lsra.cpp b/src/jit/lsra.cpp index 36007b8407..867858459d 100644 --- a/src/jit/lsra.cpp +++ b/src/jit/lsra.cpp @@ -3366,15 +3366,8 @@ bool LinearScan::isSpillCandidate(Interval* current, #endif { RefPosition* nextPhysRegPosition = physRegRecord->getNextRefPosition(); -#ifdef _TARGET_ARM64_ - // On ARM64, we may need to actually allocate IP0 and IP1 in some cases, but we don't include it in - // the allocation order for tryAllocateFreeReg. - if ((physRegRecord->regNum != REG_IP0) && (physRegRecord->regNum != REG_IP1)) -#endif // _TARGET_ARM64_ - { - assert((nextPhysRegPosition != nullptr) && (nextPhysRegPosition->nodeLocation == refLocation) && - (candidateBit != refPosition->registerAssignment)); - } + assert((nextPhysRegPosition != nullptr) && (nextPhysRegPosition->nodeLocation == refLocation) && + (candidateBit != refPosition->registerAssignment)); return false; } |