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| author | Steve MacLean <sdmaclea.qdt@qualcommdatacenter.com> | 2017-10-19 17:43:11 -0400 |
|---|---|---|
| committer | Steve MacLean <sdmaclea.qdt@qualcommdatacenter.com> | 2017-10-20 17:07:01 -0400 |
| commit | 8883f2241425e9a74611e667ac1a1af9c4c9a7bc (patch) | |
| tree | e45b1ce975af0e6be0029fa453ea0ed121c8e49d /src/jit/instrsarm64.h | |
| parent | ae991c3a6042256c25d6c82e2714cd41eb14798a (diff) | |
| download | coreclr-8883f2241425e9a74611e667ac1a1af9c4c9a7bc.tar.gz coreclr-8883f2241425e9a74611e667ac1a1af9c4c9a7bc.tar.bz2 coreclr-8883f2241425e9a74611e667ac1a1af9c4c9a7bc.zip | |
[Arm64] Add more SIMD instructions
Diffstat (limited to 'src/jit/instrsarm64.h')
| -rw-r--r-- | src/jit/instrsarm64.h | 27 |
1 files changed, 22 insertions, 5 deletions
diff --git a/src/jit/instrsarm64.h b/src/jit/instrsarm64.h index fc2b44f197..433bde7f5f 100644 --- a/src/jit/instrsarm64.h +++ b/src/jit/instrsarm64.h @@ -622,6 +622,11 @@ INST2(ctst, "ctst", 0, 0, IF_EN2O, 0x5EE08C00, 0x0E208C00) // ctst Vd,Vn,Vm DV_3E 01011110111mmmmm 100011nnnnnddddd 5EE0 8C00 Vd,Vn,Vm (scalar) // ctst Vd,Vn,Vm DV_3A 0Q001110XX1mmmmm 100011nnnnnddddd 0E20 8C00 Vd,Vn,Vm (vector) +// enum name FP LD/ST DV_2G DV_3B +INST2(faddp, "faddp", 0, 0, IF_EN2P, 0x7E30D800, 0x2E20D400) + // faddp Vd,Vn DV_2G 011111100X110000 110110nnnnnddddd 7E30 D800 Vd,Vn (scalar) + // faddp Vd,Vn,Vm DV_3B 0Q1011100X1mmmmm 110101nnnnnddddd 2E20 D400 Vd,Vn,Vm (vector) + INST1(ldar, "ldar", 0,LD, IF_LS_2A, 0x88DFFC00) // ldar Rt,[Xn] LS_2A 1X00100011011111 111111nnnnnttttt 88DF FC00 @@ -983,7 +988,7 @@ INST1(bif, "bif", 0, 0, IF_DV_3C, 0x2EE01C00) // bif Vd,Vn,Vm DV_3C 0Q101110111mmmmm 000111nnnnnddddd 2EE0 1C00 Vd,Vn,Vm INST1(addv, "addv", 0, 0, IF_DV_2M, 0x0E31B800) - // addv Vd,Vn,imm DV_2M 0Q001110XX110001 101110nnnnnddddd 0E31 B800 Vd,Vn (vector) + // addv Vd,Vn DV_2M 0Q001110XX110001 101110nnnnnddddd 0E31 B800 Vd,Vn (vector) INST1(cnt, "cnt", 0, 0, IF_DV_2M, 0x0E205800) // cnt Vd,Vn DV_2M 0Q00111000100000 010110nnnnnddddd 0E20 5800 Vd,Vn (vector) @@ -992,16 +997,28 @@ INST1(not, "not", 0, 0, IF_DV_2M, 0x2E205800) // not Vd,Vn DV_2M 0Q10111000100000 010110nnnnnddddd 2E20 5800 Vd,Vn (vector) INST1(saddlv, "saddlv", 0, 0, IF_DV_2M, 0x0E303800) - // saddlv Vd,Vn,imm DV_2M 0Q001110XX110000 001110nnnnnddddd 0E30 3800 Vd,Vn (vector) + // saddlv Vd,Vn DV_2M 0Q001110XX110000 001110nnnnnddddd 0E30 3800 Vd,Vn (vector) + +INST1(smaxv, "smaxv", 0, 0, IF_DV_2M, 0x0E30A800) + // smaxv Vd,Vn DV_2M 0Q001110XX110000 101010nnnnnddddd 0E30 A800 Vd,Vn (vector) + +INST1(sminv, "sminv", 0, 0, IF_DV_2M, 0x0E31A800) + // sminv Vd,Vn DV_2M 0Q001110XX110001 101010nnnnnddddd 0E31 A800 Vd,Vn (vector) INST1(uaddlv, "uaddlv", 0, 0, IF_DV_2M, 0x2E303800) - // uaddlv Vd,Vn,imm DV_2M 0Q101110XX110000 001110nnnnnddddd 2E30 3800 Vd,Vn (vector) + // uaddlv Vd,Vn DV_2M 0Q101110XX110000 001110nnnnnddddd 2E30 3800 Vd,Vn (vector) + +INST1(umaxv, "umaxv", 0, 0, IF_DV_2M, 0x2E30A800) + // umaxv Vd,Vn DV_2M 0Q101110XX110000 101010nnnnnddddd 2E30 A800 Vd,Vn (vector) + +INST1(uminv, "uminv", 0, 0, IF_DV_2M, 0x2E31A800) + // uminv Vd,Vn DV_2M 0Q101110XX110001 101010nnnnnddddd 2E31 A800 Vd,Vn (vector) INST1(xtn, "xtn", 0, 0, IF_DV_2M, 0x0E212800) - // xtn Vd,Vn,imm DV_2M 00101110XX110000 001110nnnnnddddd 0E21 2800 Vd,Vn (vector) + // xtn Vd,Vn DV_2M 00101110XX110000 001110nnnnnddddd 0E21 2800 Vd,Vn (vector) INST1(xtn2, "xtn2", 0, 0, IF_DV_2M, 0x4E212800) - // xtn Vd,Vn,imm DV_2M 01101110XX110000 001110nnnnnddddd 4E21 2800 Vd,Vn (vector) + // xtn2 Vd,Vn DV_2M 01101110XX110000 001110nnnnnddddd 4E21 2800 Vd,Vn (vector) INST1(fnmul, "fnmul", 0, 0, IF_DV_3D, 0x1E208800) // fnmul Vd,Vn,Vm DV_3D 000111100X1mmmmm 100010nnnnnddddd 1E20 8800 Vd,Vn,Vm (scalar) |