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| author | Kyungwoo Lee <kyulee@microsoft.com> | 2016-04-29 10:29:28 -0700 |
|---|---|---|
| committer | Kyungwoo Lee <kyulee@microsoft.com> | 2016-04-29 14:52:46 -0700 |
| commit | 45798f661f8c8c042f3582cde8b611d1c9c7343f (patch) | |
| tree | 0d75dad9935f95c5bf4bd309899a37456e4478bd /src/jit/instrsarm64.h | |
| parent | 601b1051c1022d5f764224e35be59f02a6074ad0 (diff) | |
| download | coreclr-45798f661f8c8c042f3582cde8b611d1c9c7343f.tar.gz coreclr-45798f661f8c8c042f3582cde8b611d1c9c7343f.tar.bz2 coreclr-45798f661f8c8c042f3582cde8b611d1c9c7343f.zip | |
ARM64: Enabling Crossgen End-to-End Mscorlib
Fixes https://github.com/dotnet/coreclr/issues/4350
Fixes https://github.com/dotnet/coreclr/issues/4615
This is a bit large change across VM/Zap/JIT to properly support crossgen
scenario.
1. Fix incorrect `ldr` encoding with size.
2. Enforce JIT data following JIT code per method by allocating them together.
This guarantees correct PC-relative encoding for such constant data access
without fix-up.
3. For the general fix-up data acceess, use `adrp/add` instruction pairs with fix-ups.
Two more relocations types are implemented in all sides.
4. Interface dispatch stub is now implemented which is needed for
interface call for crossgen.
I've verified hello world runs with mscorlib.ni.dll.
Diffstat (limited to 'src/jit/instrsarm64.h')
| -rw-r--r-- | src/jit/instrsarm64.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/jit/instrsarm64.h b/src/jit/instrsarm64.h index 21fddc5fe7..51ec30e0db 100644 --- a/src/jit/instrsarm64.h +++ b/src/jit/instrsarm64.h @@ -91,7 +91,7 @@ INST5(ldr, "ldr", 0,LD, IF_EN5A, 0xB9400000, 0xB9400000, 0xB8400000, // ldr Rt,[Xn+pimm12] LS_2B 1X11100101iiiiii iiiiiinnnnnttttt B940 0000 imm(0-4095<<{2,3}) // ldr Rt,[Xn+simm9] LS_2C 1X111000010iiiii iiiiPPnnnnnttttt B840 0000 [Xn imm(-256..+255) pre/post/no inc] // ldr Rt,[Xn,(Rm,ext,shl)] LS_3A 1X111000011mmmmm oooS10nnnnnttttt B860 0800 [Xn, ext(Rm) LSL {0,2,3}] - // ldr Vt/Rt,[PC+simm19<<2] LS_1A XX011000iiiiiiii iiiiiiiiiiittttt 1800 0000 [PC +- imm(1MB)] + // ldr Vt/Rt,[PC+simm19<<2] LS_1A XX011V00iiiiiiii iiiiiiiiiiittttt 1800 0000 [PC +- imm(1MB)] INST5(ldrsw, "ldrsw", 0,LD, IF_EN5A, 0xB9800000, 0xB9800000, 0xB8800000, 0xB8A00800, 0x98000000) // ldrsw Rt,[Xn] LS_2A 1011100110000000 000000nnnnnttttt B980 0000 |