ARM64: Revisit for Fix GC hole in indirect call site

This fixes https://github.com/dotnet/coreclr/issues/3738.
The fix I made in
https://github.com/dotnet/coreclr/commit/4dfd323dab88b902fc9479efa60cb5d6b7659e94
 used 3rd/4th operand to keep GC info, which actually conflicts with
 address field which is unioned with these operands.
So, I go back to the original fix that I proposed below:

Indirect call (```br``` or ```blr```) target is encoded with a register
which the first operand internally represents.
Unfortunately, call sites use the first two operands to hold GC callee-save registers.
So, this GC register information was overridden by the call target operand
in the indirect(virtual) call sites.
The fix is to split branch instruction categories for these two instructions
while keeping ```ret``` same as before. They internally use the third
operand to encode the target since the first two are used for GC info.
The reason I didn't change ```ret``` is because the return instruction
is created as a small instruction (not using operand 3 and more).

1 files changed, 0 insertions, 3 deletions

diff --git a/src/jit/emit.h b/src/jit/emit.h
index c35532233e..39241278a5 100644
--- a/src/jit/emit.h
+++ b/src/jit/emit.h
@@ -942,9 +942,6 @@ protected:
                 iiaEncodedInstrCount = (count << iaut_SHIFT) | iaut_INST_COUNT;
             }
 
-            // Note that we use the _idReg3 and _idReg4 fields to hold
-            // the live gcrefReg mask for the call instructions on arm64
-            //
             struct
             {
                 regNumber    _idReg3       :REGNUM_BITS;