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| author | Carol Eidt <carol.eidt@microsoft.com> | 2019-05-16 09:25:00 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-16 09:25:00 -0700 |
| commit | fb2aa6725dd7e5610c5589bc464f9a67470faaf9 (patch) | |
| tree | 4d738465b19e15e113b5028eef14cf1dd708f67b /src/jit/codegenxarch.cpp | |
| parent | ff61bfc8aa9f0f71feddc8c03d824b13cc61215c (diff) | |
| download | coreclr-fb2aa6725dd7e5610c5589bc464f9a67470faaf9.tar.gz coreclr-fb2aa6725dd7e5610c5589bc464f9a67470faaf9.tar.bz2 coreclr-fb2aa6725dd7e5610c5589bc464f9a67470faaf9.zip | |
Ensure that SIMD fields are correctly typed (#24377)
When a struct field is imported, its type needs to be normalized.
Also, the LHS of a struct init, even if a SIMD type, should not be transformed to a non-block node,
except in the case of a SIMD local, in which case it must be transformed to a simple assignment.
Also, add an assert to catch this kind of bug in liveness.
Fix #24336
Diffstat (limited to 'src/jit/codegenxarch.cpp')
| -rw-r--r-- | src/jit/codegenxarch.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/jit/codegenxarch.cpp b/src/jit/codegenxarch.cpp index 2c04b380f2..7a67043dfc 100644 --- a/src/jit/codegenxarch.cpp +++ b/src/jit/codegenxarch.cpp @@ -4672,6 +4672,8 @@ void CodeGen::genCodeForStoreLclVar(GenTreeLclVar* tree) return; } + // TODO-CQ: It would be better to simply contain the zero, rather than + // generating zero into a register. if (varTypeIsSIMD(targetType) && (targetReg != REG_NA) && op1->IsCnsIntOrI()) { // This is only possible for a zero-init. |