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author | Fei Peng <fei.peng@intel.com> | 2018-01-09 16:57:07 -0800 |
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committer | Fei Peng <fei.peng@intel.com> | 2018-01-09 16:57:07 -0800 |
commit | 2267b5d8675b7316d32a14c76ee992a2aac4a123 (patch) | |
tree | c019f881cd7032231af93ce42c29aa92a1261fa1 /netci.groovy | |
parent | cab0db6345a7941f75d991281bcc0079d28ba182 (diff) | |
download | coreclr-2267b5d8675b7316d32a14c76ee992a2aac4a123.tar.gz coreclr-2267b5d8675b7316d32a14c76ee992a2aac4a123.tar.bz2 coreclr-2267b5d8675b7316d32a14c76ee992a2aac4a123.zip |
Add new CI mode for Intel HW intrinsics
Diffstat (limited to 'netci.groovy')
-rwxr-xr-x | netci.groovy | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/netci.groovy b/netci.groovy index 321d267f10..ad6f8bba99 100755 --- a/netci.groovy +++ b/netci.groovy @@ -86,6 +86,11 @@ class Constants { 'tailcallstress' : ['COMPlus_TailcallStress' : '1'], 'jitsse2only' : ['COMPlus_EnableAVX' : '0', 'COMPlus_EnableSSE3_4' : '0'], 'jitnosimd' : ['COMPlus_FeatureSIMD' : '0'], + 'jitincompletehwintrinsic' : ['COMPlus_EnableIncompleteISAClass' : '1'], + 'jitx86hwintrinsicnoavx' : ['COMPlus_EnableIncompleteISAClass' : '1', 'COMPlus_EnableAVX' : '0'], // testing the legacy SSE encoding + 'jitx86hwintrinsicnoavx2' : ['COMPlus_EnableIncompleteISAClass' : '1', 'COMPlus_EnableAVX2' : '0'], // testing SNB/IVB + 'jitx86hwintrinsicnosimd' : ['COMPlus_EnableIncompleteISAClass' : '1', 'COMPlus_FeatureSIMD' : '0'], // match "jitnosimd", may need to remove after decoupling HW intrinsic from FeatureSIMD + 'jitnox86hwintrinsic' : ['COMPlus_EnableIncompleteISAClass' : '1', 'COMPlus_EnableSSE' : '0' , 'COMPlus_EnableSSE2' : '0' , 'COMPlus_EnableSSE3' : '0' , 'COMPlus_EnableSSSE3' : '0' , 'COMPlus_EnableSSE41' : '0' , 'COMPlus_EnableSSE42' : '0' , 'COMPlus_EnableAVX' : '0' , 'COMPlus_EnableAVX2' : '0' , 'COMPlus_EnableAES' : '0' , 'COMPlus_EnableBMI1' : '0' , 'COMPlus_EnableBMI2' : '0' , 'COMPlus_EnableFMA' : '0' , 'COMPlus_EnableLZCNT' : '0' , 'COMPlus_EnablePCLMULQDQ' : '0' , 'COMPlus_EnablePOPCNT' : '0'], 'corefx_baseline' : [ : ], // corefx baseline 'corefx_minopts' : ['COMPlus_JITMinOpts' : '1'], 'corefx_tieredcompilation' : ['COMPlus_EXPERIMENTAL_TieredCompilation' : '1'], @@ -981,6 +986,11 @@ def static addNonPRTriggers(def job, def branch, def isPR, def architecture, def case 'tailcallstress': case 'jitsse2only': case 'jitnosimd': + case 'jitnox86hwintrinsic': + case 'jitincompletehwintrinsic': + case 'jitx86hwintrinsicnoavx': + case 'jitx86hwintrinsicnoavx2': + case 'jitx86hwintrinsicnosimd': case 'corefx_baseline': case 'corefx_minopts': case 'corefx_jitstress1': |