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author | Hyeongseok Oh <hseok82.oh@samsung.com> | 2017-03-20 15:26:33 +0900 |
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committer | Hyeongseok Oh <hseok82.oh@samsung.com> | 2017-03-20 16:43:47 +0900 |
commit | dd130b56246b8854fb711bcb32839b398eb240ee (patch) | |
tree | 8e98bca98d796b9ea9ce0ae06b7779f31f4e53f7 | |
parent | d905f67f12c6b2eed918894e0642ec972a1d9fec (diff) | |
download | coreclr-dd130b56246b8854fb711bcb32839b398eb240ee.tar.gz coreclr-dd130b56246b8854fb711bcb32839b398eb240ee.tar.bz2 coreclr-dd130b56246b8854fb711bcb32839b398eb240ee.zip |
[ARM32/Linux] Fix register allocation for null check in call instruction
Fix assertion when two temporary registers are reserved in call instruction
-rw-r--r-- | src/jit/codegenarm.cpp | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/jit/codegenarm.cpp b/src/jit/codegenarm.cpp index e276b711c5..b5e3313443 100644 --- a/src/jit/codegenarm.cpp +++ b/src/jit/codegenarm.cpp @@ -1952,8 +1952,13 @@ void CodeGen::genCallInstruction(GenTreeCall* call) // Insert a null check on "this" pointer if asked. if (call->NeedsNullCheck()) { - const regNumber regThis = genGetThisArgReg(call); - const regNumber tmpReg = genRegNumFromMask(call->gtRsvdRegs); + const regNumber regThis = genGetThisArgReg(call); + regMaskTP tempMask = genFindLowestBit(call->gtRsvdRegs); + const regNumber tmpReg = genRegNumFromMask(tempMask); + if (genCountBits(call->gtRsvdRegs) > 1) + { + call->gtRsvdRegs &= ~tempMask; + } getEmitter()->emitIns_R_R_I(INS_ldr, EA_4BYTE, tmpReg, regThis, 0); } |