Revert "Delete unused variables in jit. Part 2. (#23481)" (#23488)

This reverts commit 6cb120cc74ca61fc314e3cc43007778d2aafd041.

12 files changed, 147 insertions, 68 deletions

diff --git a/src/jit/emitarm64.cpp b/src/jit/emitarm64.cpp
index afd5cf44e2..d066edfd27 100644
--- a/src/jit/emitarm64.cpp
+++ b/src/jit/emitarm64.cpp
@@ -2327,9 +2327,9 @@ emitter::code_t emitter::emitInsCode(instruction ins, insFormat fmt)
     unsigned R = bmImm.immR;
     unsigned S = bmImm.immS;
 
-    unsigned elemWidth = 64; // used when N == 1
+    unsigned elemWidth = 64; // used when immN == 1
 
-    if (N == 0) // find the smaller elemWidth when N == 0
+    if (bmImm.immN == 0) // find the smaller elemWidth when immN == 0
     {
         // Scan S for the highest bit not set
         elemWidth = 32;
@@ -3393,8 +3393,9 @@ void emitter::emitIns_I(instruction ins, emitAttr attr, ssize_t imm)
 
 void emitter::emitIns_R(instruction ins, emitAttr attr, regNumber reg)
 {
-    insFormat  fmt = IF_NONE;
-    instrDesc* id  = nullptr;
+    emitAttr   size = EA_SIZE(attr);
+    insFormat  fmt  = IF_NONE;
+    instrDesc* id   = nullptr;
 
     /* Figure out the encoding format of the instruction */
     switch (ins)
@@ -3536,6 +3537,7 @@ void emitter::emitIns_R_I(instruction ins, emitAttr attr, regNumber reg, ssize_t
                 ssize_t  imm8 = 0;
                 unsigned pos  = 0;
                 canEncode     = true;
+                bool failed   = false;
                 while (uimm != 0)
                 {
                     INT64 loByte = uimm & 0xFF;
@@ -6087,7 +6089,8 @@ void emitter::emitIns_R_R_R_R(
 
 void emitter::emitIns_R_COND(instruction ins, emitAttr attr, regNumber reg, insCond cond)
 {
-    insFormat    fmt = IF_NONE;
+    emitAttr     size = EA_SIZE(attr);
+    insFormat    fmt  = IF_NONE;
     condFlagsImm cfi;
     cfi.immCFVal = 0;
 
@@ -6129,7 +6132,8 @@ void emitter::emitIns_R_COND(instruction ins, emitAttr attr, regNumber reg, insC
 
 void emitter::emitIns_R_R_COND(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, insCond cond)
 {
-    insFormat    fmt = IF_NONE;
+    emitAttr     size = EA_SIZE(attr);
+    insFormat    fmt  = IF_NONE;
     condFlagsImm cfi;
     cfi.immCFVal = 0;
 
@@ -6174,7 +6178,8 @@ void emitter::emitIns_R_R_COND(instruction ins, emitAttr attr, regNumber reg1, r
 void emitter::emitIns_R_R_R_COND(
     instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3, insCond cond)
 {
-    insFormat    fmt = IF_NONE;
+    emitAttr     size = EA_SIZE(attr);
+    insFormat    fmt  = IF_NONE;
     condFlagsImm cfi;
     cfi.immCFVal = 0;
 
@@ -6224,7 +6229,8 @@ void emitter::emitIns_R_R_R_COND(
 void emitter::emitIns_R_R_FLAGS_COND(
     instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, insCflags flags, insCond cond)
 {
-    insFormat    fmt = IF_NONE;
+    emitAttr     size = EA_SIZE(attr);
+    insFormat    fmt  = IF_NONE;
     condFlagsImm cfi;
     cfi.immCFVal = 0;
 
@@ -6268,7 +6274,8 @@ void emitter::emitIns_R_R_FLAGS_COND(
 void emitter::emitIns_R_I_FLAGS_COND(
     instruction ins, emitAttr attr, regNumber reg, int imm, insCflags flags, insCond cond)
 {
-    insFormat    fmt = IF_NONE;
+    emitAttr     size = EA_SIZE(attr);
+    insFormat    fmt  = IF_NONE;
     condFlagsImm cfi;
     cfi.immCFVal = 0;
 
@@ -6869,6 +6876,7 @@ void emitter::emitIns_R_C(
 
     emitAttr      size = EA_SIZE(attr);
     insFormat     fmt  = IF_NONE;
+    int           disp = 0;
     instrDescJmp* id   = emitNewInstrJmp();
 
     switch (ins)
@@ -9063,13 +9071,14 @@ unsigned emitter::emitOutputCall(insGroup* ig, BYTE* dst, instrDesc* id, code_t
 
 size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
 {
-    BYTE*       dst  = *dp;
-    BYTE*       odst = dst;
-    code_t      code = 0;
-    size_t      sz   = emitGetInstrDescSize(id); // TODO-ARM64-Cleanup: on ARM, this is set in each case. why?
-    instruction ins  = id->idIns();
-    insFormat   fmt  = id->idInsFmt();
-    emitAttr    size = id->idOpSize();
+    BYTE*         dst  = *dp;
+    BYTE*         odst = dst;
+    code_t        code = 0;
+    size_t        sz   = emitGetInstrDescSize(id); // TODO-ARM64-Cleanup: on ARM, this is set in each case. why?
+    instruction   ins  = id->idIns();
+    insFormat     fmt  = id->idInsFmt();
+    emitAttr      size = id->idOpSize();
+    unsigned char callInstrSize = 0;
 
 #ifdef DEBUG
 #if DUMP_GC_TABLES
@@ -9081,6 +9090,8 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
 
     assert(REG_NA == (int)REG_NA);
 
+    VARSET_TP GCvars(VarSetOps::UninitVal());
+
     /* What instruction format have we got? */
 
     switch (fmt)
@@ -11694,6 +11705,8 @@ void emitter::emitInsLoadStoreOp(instruction ins, emitAttr attr, regNumber dataR
 
 regNumber emitter::emitInsBinary(instruction ins, emitAttr attr, GenTree* dst, GenTree* src)
 {
+    regNumber result = REG_NA;
+
     // dst can only be a reg
     assert(!dst->isContained());
 
@@ -11724,6 +11737,8 @@ regNumber emitter::emitInsBinary(instruction ins, emitAttr attr, GenTree* dst, G
 
 regNumber emitter::emitInsTernary(instruction ins, emitAttr attr, GenTree* dst, GenTree* src1, GenTree* src2)
 {
+    regNumber result = REG_NA;
+
     // dst can only be a reg
     assert(!dst->isContained());
 
diff --git a/src/jit/hwintrinsiccodegenxarch.cpp b/src/jit/hwintrinsiccodegenxarch.cpp
index dc452e5d7b..aa30f76a1d 100644
--- a/src/jit/hwintrinsiccodegenxarch.cpp
+++ b/src/jit/hwintrinsiccodegenxarch.cpp
@@ -89,10 +89,11 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
 
     if (genIsTableDrivenHWIntrinsic(intrinsicId, category))
     {
-        GenTree*  op1       = node->gtGetOp1();
-        GenTree*  op2       = node->gtGetOp2();
-        regNumber targetReg = node->gtRegNum;
-        var_types baseType  = node->gtSIMDBaseType;
+        GenTree*  op1        = node->gtGetOp1();
+        GenTree*  op2        = node->gtGetOp2();
+        regNumber targetReg  = node->gtRegNum;
+        var_types targetType = node->TypeGet();
+        var_types baseType   = node->gtSIMDBaseType;
 
         regNumber op1Reg = REG_NA;
         regNumber op2Reg = REG_NA;
@@ -383,10 +384,11 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
 //
 void CodeGen::genHWIntrinsic_R_RM(GenTreeHWIntrinsic* node, instruction ins, emitAttr attr)
 {
-    regNumber targetReg = node->gtRegNum;
-    GenTree*  op1       = node->gtGetOp1();
-    GenTree*  op2       = node->gtGetOp2();
-    emitter*  emit      = getEmitter();
+    var_types targetType = node->TypeGet();
+    regNumber targetReg  = node->gtRegNum;
+    GenTree*  op1        = node->gtGetOp1();
+    GenTree*  op2        = node->gtGetOp2();
+    emitter*  emit       = getEmitter();
 
     if (op2 != nullptr)
     {
@@ -521,10 +523,11 @@ void CodeGen::genHWIntrinsic_R_RM(GenTreeHWIntrinsic* node, instruction ins, emi
 //
 void CodeGen::genHWIntrinsic_R_RM_I(GenTreeHWIntrinsic* node, instruction ins, int8_t ival)
 {
-    regNumber targetReg = node->gtRegNum;
-    GenTree*  op1       = node->gtGetOp1();
-    emitAttr  simdSize  = EA_ATTR(node->gtSIMDSize);
-    emitter*  emit      = getEmitter();
+    var_types targetType = node->TypeGet();
+    regNumber targetReg  = node->gtRegNum;
+    GenTree*  op1        = node->gtGetOp1();
+    emitAttr  simdSize   = EA_ATTR(node->gtSIMDSize);
+    emitter*  emit       = getEmitter();
 
     // TODO-XArch-CQ: Commutative operations can have op1 be contained
     // TODO-XArch-CQ: Non-VEX encoded instructions can have both ops contained
@@ -714,11 +717,12 @@ void CodeGen::genHWIntrinsic_R_R_RM(
 //
 void CodeGen::genHWIntrinsic_R_R_RM_I(GenTreeHWIntrinsic* node, instruction ins, int8_t ival)
 {
-    regNumber targetReg = node->gtRegNum;
-    GenTree*  op1       = node->gtGetOp1();
-    GenTree*  op2       = node->gtGetOp2();
-    emitAttr  simdSize  = EA_ATTR(node->gtSIMDSize);
-    emitter*  emit      = getEmitter();
+    var_types targetType = node->TypeGet();
+    regNumber targetReg  = node->gtRegNum;
+    GenTree*  op1        = node->gtGetOp1();
+    GenTree*  op2        = node->gtGetOp2();
+    emitAttr  simdSize   = EA_ATTR(node->gtSIMDSize);
+    emitter*  emit       = getEmitter();
 
     // TODO-XArch-CQ: Commutative operations can have op1 be contained
     // TODO-XArch-CQ: Non-VEX encoded instructions can have both ops contained
@@ -869,12 +873,13 @@ void CodeGen::genHWIntrinsic_R_R_RM_I(GenTreeHWIntrinsic* node, instruction ins,
 //
 void CodeGen::genHWIntrinsic_R_R_RM_R(GenTreeHWIntrinsic* node, instruction ins)
 {
-    regNumber targetReg = node->gtRegNum;
-    GenTree*  op1       = node->gtGetOp1();
-    GenTree*  op2       = node->gtGetOp2();
-    GenTree*  op3       = nullptr;
-    emitAttr  simdSize  = EA_ATTR(node->gtSIMDSize);
-    emitter*  emit      = getEmitter();
+    var_types targetType = node->TypeGet();
+    regNumber targetReg  = node->gtRegNum;
+    GenTree*  op1        = node->gtGetOp1();
+    GenTree*  op2        = node->gtGetOp2();
+    GenTree*  op3        = nullptr;
+    emitAttr  simdSize   = EA_ATTR(node->gtSIMDSize);
+    emitter*  emit       = getEmitter();
 
     assert(op1->OperIsList());
     assert(op2 == nullptr);
@@ -1151,6 +1156,7 @@ void CodeGen::genHWIntrinsicJumpTableFallback(NamedIntrinsic            intrinsi
     BasicBlock* jmpTable[256];
 
     unsigned jmpTableBase = emit->emitBBTableDataGenBeg(maxByte, true);
+    unsigned jmpTableOffs = 0;
 
     // Emit the jump table
     for (unsigned i = 0; i < maxByte; i++)
@@ -1327,10 +1333,16 @@ void CodeGen::genSSEIntrinsic(GenTreeHWIntrinsic* node)
     NamedIntrinsic intrinsicId = node->gtHWIntrinsicId;
     GenTree*       op1         = node->gtGetOp1();
     GenTree*       op2         = node->gtGetOp2();
+    GenTree*       op3         = nullptr;
+    GenTree*       op4         = nullptr;
     regNumber      targetReg   = node->gtRegNum;
+    var_types      targetType  = node->TypeGet();
     var_types      baseType    = node->gtSIMDBaseType;
 
     regNumber op1Reg = REG_NA;
+    regNumber op2Reg = REG_NA;
+    regNumber op3Reg = REG_NA;
+    regNumber op4Reg = REG_NA;
     emitter*  emit   = getEmitter();
 
     genConsumeHWIntrinsicOperands(node);
@@ -1694,10 +1706,16 @@ void CodeGen::genSSE41Intrinsic(GenTreeHWIntrinsic* node)
     NamedIntrinsic intrinsicId = node->gtHWIntrinsicId;
     GenTree*       op1         = node->gtGetOp1();
     GenTree*       op2         = node->gtGetOp2();
+    GenTree*       op3         = nullptr;
+    GenTree*       op4         = nullptr;
     regNumber      targetReg   = node->gtRegNum;
+    var_types      targetType  = node->TypeGet();
     var_types      baseType    = node->gtSIMDBaseType;
 
     regNumber op1Reg = REG_NA;
+    regNumber op2Reg = REG_NA;
+    regNumber op3Reg = REG_NA;
+    regNumber op4Reg = REG_NA;
     emitter*  emit   = getEmitter();
 
     genConsumeHWIntrinsicOperands(node);
diff --git a/src/jit/lower.cpp b/src/jit/lower.cpp
index 4189dcee66..fc507c4c50 100644
--- a/src/jit/lower.cpp
+++ b/src/jit/lower.cpp
@@ -496,6 +496,8 @@ GenTree* Lowering::LowerSwitch(GenTree* node)
     noway_assert(jumpCnt >= 2);
 
     // Spill the argument to the switch node into a local so that it can be used later.
+    unsigned blockWeight = originalSwitchBB->getBBWeight(comp);
+
     LIR::Use use(switchBBRange, &(node->gtOp.gtOp1), node);
     ReplaceWithLclVar(use);
 
@@ -506,8 +508,9 @@ GenTree* Lowering::LowerSwitch(GenTree* node)
     assert(node->gtOper == GT_SWITCH);
     GenTree* temp = node->gtOp.gtOp1;
     assert(temp->gtOper == GT_LCL_VAR);
-    unsigned  tempLclNum  = temp->gtLclVarCommon.gtLclNum;
-    var_types tempLclType = temp->TypeGet();
+    unsigned   tempLclNum  = temp->gtLclVarCommon.gtLclNum;
+    LclVarDsc* tempVarDsc  = comp->lvaTable + tempLclNum;
+    var_types  tempLclType = temp->TypeGet();
 
     BasicBlock* defaultBB   = jumpTab[jumpCnt - 1];
     BasicBlock* followingBB = originalSwitchBB->bbNext;
@@ -2041,7 +2044,8 @@ void Lowering::LowerFastTailCall(GenTreeCall* call)
                 // This should not be a GT_PHI_ARG.
                 assert(treeNode->OperGet() != GT_PHI_ARG);
 
-                GenTreeLclVarCommon* lcl = treeNode->AsLclVarCommon();
+                GenTreeLclVarCommon* lcl    = treeNode->AsLclVarCommon();
+                LclVarDsc*           lclVar = &comp->lvaTable[lcl->gtLclNum];
 
                 // Fast tail calling criteria permits passing of structs of size 1, 2, 4 and 8 as args.
                 // It is possible that the callerArgLclNum corresponds to such a struct whose stack slot
@@ -2562,11 +2566,11 @@ GenTree* Lowering::OptimizeConstCompare(GenTree* cmp)
 
 #if defined(_TARGET_XARCH_) || defined(_TARGET_ARM64_)
     GenTree*       op1      = cmp->gtGetOp1();
+    var_types      op1Type  = op1->TypeGet();
     GenTreeIntCon* op2      = cmp->gtGetOp2()->AsIntCon();
     ssize_t        op2Value = op2->IconValue();
 
 #ifdef _TARGET_XARCH_
-    var_types op1Type = op1->TypeGet();
     if (IsContainableMemoryOp(op1) && varTypeIsSmall(op1Type) && genSmallTypeCanRepresentValue(op1Type, op2Value))
     {
         //
@@ -3837,6 +3841,7 @@ GenTree* Lowering::LowerNonvirtPinvokeCall(GenTreeCall* call)
     // platform. They may be changed in the future such that they preserve all register values.
 
     GenTree* result = nullptr;
+    void*    addr   = nullptr;
 
     // assert we have seen one of these
     noway_assert(comp->info.compCallUnmanaged != 0);
@@ -4188,6 +4193,8 @@ bool Lowering::AreSourcesPossiblyModifiedLocals(GenTree* addr, GenTree* base, Ge
 {
     assert(addr != nullptr);
 
+    unsigned markCount = 0;
+
     SideEffectSet baseSideEffects;
     if (base != nullptr)
     {
@@ -4335,6 +4342,8 @@ GenTree* Lowering::TryCreateAddrMode(LIR::Use&& use, bool isIndir)
         return addr;
     }
 
+    GenTree* arrLength = nullptr;
+
     JITDUMP("Addressing mode:\n");
     JITDUMP("  Base\n    ");
     DISPNODE(base);
@@ -4394,6 +4403,8 @@ GenTree* Lowering::TryCreateAddrMode(LIR::Use&& use, bool isIndir)
 //
 GenTree* Lowering::LowerAdd(GenTree* node)
 {
+    GenTree* next = node->gtNext;
+
 #ifndef _TARGET_ARMARCH_
     if (varTypeIsIntegralOrI(node))
     {
@@ -4448,6 +4459,7 @@ bool Lowering::LowerUnsignedDivOrMod(GenTreeOp* divMod)
     assert(divMod->OperGet() != GT_UMOD);
 #endif // _TARGET_ARM64_
 
+    GenTree* next     = divMod->gtNext;
     GenTree* dividend = divMod->gtGetOp1();
     GenTree* divisor  = divMod->gtGetOp2();
 
@@ -4821,6 +4833,9 @@ GenTree* Lowering::LowerConstIntDivOrMod(GenTree* node)
 
     // We need to use the dividend node multiple times so its value needs to be
     // computed once and stored in a temp variable.
+
+    unsigned curBBWeight = comp->compCurBB->getBBWeight(comp);
+
     LIR::Use opDividend(BlockRange(), &divMod->gtOp.gtOp1, divMod);
     dividend = ReplaceWithLclVar(opDividend);
 
@@ -4897,7 +4912,10 @@ GenTree* Lowering::LowerConstIntDivOrMod(GenTree* node)
 GenTree* Lowering::LowerSignedDivOrMod(GenTree* node)
 {
     assert((node->OperGet() == GT_DIV) || (node->OperGet() == GT_MOD));
-    GenTree* next = node->gtNext;
+    GenTree* next     = node->gtNext;
+    GenTree* divMod   = node;
+    GenTree* dividend = divMod->gtGetOp1();
+    GenTree* divisor  = divMod->gtGetOp2();
 
     if (varTypeIsIntegral(node->TypeGet()))
     {
@@ -5054,8 +5072,9 @@ void Lowering::WidenSIMD12IfNecessary(GenTreeLclVarCommon* node)
 GenTree* Lowering::LowerArrElem(GenTree* node)
 {
     // This will assert if we don't have an ArrElem node
-    GenTreeArrElem*     arrElem = node->AsArrElem();
-    const unsigned char rank    = arrElem->gtArrElem.gtArrRank;
+    GenTreeArrElem*     arrElem     = node->AsArrElem();
+    const unsigned char rank        = arrElem->gtArrElem.gtArrRank;
+    const unsigned      blockWeight = m_block->getBBWeight(comp);
 
     JITDUMP("Lowering ArrElem\n");
     JITDUMP("============\n");
@@ -5074,6 +5093,8 @@ GenTree* Lowering::LowerArrElem(GenTree* node)
     GenTree* arrObjNode = arrElem->gtArrObj;
     assert(arrObjNode->IsLocal());
 
+    LclVarDsc* const varDsc = &comp->lvaTable[arrElem->gtArrObj->AsLclVarCommon()->gtLclNum];
+
     GenTree* insertionPoint = arrElem;
 
     // The first ArrOffs node will have 0 for the offset of the previous dimension.
diff --git a/src/jit/lowerarmarch.cpp b/src/jit/lowerarmarch.cpp
index 3e0d636e99..4b28ce260a 100644
--- a/src/jit/lowerarmarch.cpp
+++ b/src/jit/lowerarmarch.cpp
@@ -616,12 +616,15 @@ void Lowering::ContainCheckIndir(GenTreeIndir* indirNode)
     bool     makeContained = true;
     if ((addr->OperGet() == GT_LEA) && IsSafeToContainMem(indirNode, addr))
     {
+        GenTreeAddrMode* lea   = addr->AsAddrMode();
+        GenTree*         base  = lea->Base();
+        GenTree*         index = lea->Index();
+        int              cns   = lea->Offset();
+
 #ifdef _TARGET_ARM_
         // ARM floating-point load/store doesn't support a form similar to integer
         // ldr Rdst, [Rbase + Roffset] with offset in a register. The only supported
         // form is vldr Rdst, [Rbase + imm] with a more limited constraint on the imm.
-        GenTreeAddrMode* lea = addr->AsAddrMode();
-        int              cns = lea->Offset();
         if (lea->HasIndex() || !emitter::emitIns_valid_imm_for_vldst_offset(cns))
         {
             if (indirNode->OperGet() == GT_STOREIND)
@@ -867,9 +870,10 @@ void Lowering::ContainCheckSIMD(GenTreeSIMD* simdNode)
 //
 void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node)
 {
-    GenTreeArgList* argList = nullptr;
-    GenTree*        op1     = node->gtOp.gtOp1;
-    GenTree*        op2     = node->gtOp.gtOp2;
+    NamedIntrinsic  intrinsicID = node->gtHWIntrinsicId;
+    GenTreeArgList* argList     = nullptr;
+    GenTree*        op1         = node->gtOp.gtOp1;
+    GenTree*        op2         = node->gtOp.gtOp2;
 
     if (op1->OperIs(GT_LIST))
     {
diff --git a/src/jit/lowerxarch.cpp b/src/jit/lowerxarch.cpp
index a716545842..373f881a8a 100644
--- a/src/jit/lowerxarch.cpp
+++ b/src/jit/lowerxarch.cpp
@@ -145,11 +145,12 @@ void Lowering::LowerStoreIndir(GenTreeIndir* node)
 //
 void Lowering::LowerBlockStore(GenTreeBlk* blkNode)
 {
-    GenTree* dstAddr       = blkNode->Addr();
-    unsigned size          = blkNode->gtBlkSize;
-    GenTree* source        = blkNode->Data();
-    GenTree* srcAddrOrFill = nullptr;
-    bool     isInitBlk     = blkNode->OperIsInitBlkOp();
+    GenTree*  dstAddr       = blkNode->Addr();
+    unsigned  size          = blkNode->gtBlkSize;
+    GenTree*  source        = blkNode->Data();
+    Compiler* compiler      = comp;
+    GenTree*  srcAddrOrFill = nullptr;
+    bool      isInitBlk     = blkNode->OperIsInitBlkOp();
 
     if (!isInitBlk)
     {
@@ -592,6 +593,7 @@ void Lowering::LowerPutArgStk(GenTreePutArgStk* putArgStk)
     }
 
 #ifdef FEATURE_PUT_STRUCT_ARG_STK
+    GenTree* dst     = putArgStk;
     GenTree* srcAddr = nullptr;
 
     bool haveLocalAddr = false;
@@ -613,7 +615,7 @@ void Lowering::LowerPutArgStk(GenTreePutArgStk* putArgStk)
     // it might be the right thing to do.
 
     // This threshold will decide from using the helper or let the JIT decide to inline
-    // a code sequence of its choice, but currently we use CPBLK_UNROLL_LIMIT, see #20549.
+    // a code sequence of its choice.
     ssize_t helperThreshold = max(CPBLK_MOVS_LIMIT, CPBLK_UNROLL_LIMIT);
     ssize_t size            = putArgStk->gtNumSlots * TARGET_POINTER_SIZE;
 
@@ -1763,11 +1765,11 @@ void Lowering::ContainCheckDivOrMod(GenTreeOp* node)
         return;
     }
 
-    GenTree* divisor = node->gtGetOp2();
+    GenTree* dividend = node->gtGetOp1();
+    GenTree* divisor  = node->gtGetOp2();
 
     bool divisorCanBeRegOptional = true;
 #ifdef _TARGET_X86_
-    GenTree* dividend = node->gtGetOp1();
     if (dividend->OperGet() == GT_LONG)
     {
         divisorCanBeRegOptional = false;
diff --git a/src/jit/lsraarm64.cpp b/src/jit/lsraarm64.cpp
index d619c1f191..6af777ccd2 100644
--- a/src/jit/lsraarm64.cpp
+++ b/src/jit/lsraarm64.cpp
@@ -46,6 +46,7 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 int LinearScan::BuildNode(GenTree* tree)
 {
     assert(!tree->isContained());
+    Interval* prefSrcInterval = nullptr;
     int       srcCount;
     int       dstCount      = 0;
     regMaskTP dstCandidates = RBM_NONE;
@@ -55,6 +56,8 @@ int LinearScan::BuildNode(GenTree* tree)
     // Reset the build-related members of LinearScan.
     clearBuildState();
 
+    RegisterType registerType = TypeGet(tree);
+
     // Set the default dstCount. This may be modified below.
     if (tree->IsValue())
     {
@@ -600,8 +603,11 @@ int LinearScan::BuildNode(GenTree* tree)
             GenTreeBoundsChk* node = tree->AsBoundsChk();
             // Consumes arrLen & index - has no result
             assert(dstCount == 0);
-            srcCount = BuildOperandUses(node->gtIndex);
-            srcCount += BuildOperandUses(node->gtArrLen);
+
+            GenTree* intCns = nullptr;
+            GenTree* other  = nullptr;
+            srcCount        = BuildOperandUses(tree->AsBoundsChk()->gtIndex);
+            srcCount += BuildOperandUses(tree->AsBoundsChk()->gtArrLen);
         }
         break;
 
@@ -1001,6 +1007,7 @@ int LinearScan::BuildHWIntrinsic(GenTreeHWIntrinsic* intrinsicTree)
         op1 = op1->AsArgList()->Current();
     }
 
+    int  dstCount       = intrinsicTree->IsValue() ? 1 : 0;
     bool op2IsDelayFree = false;
     bool op3IsDelayFree = false;
 
diff --git a/src/jit/lsraarmarch.cpp b/src/jit/lsraarmarch.cpp
index 251bf53ab2..611d858d6d 100644
--- a/src/jit/lsraarmarch.cpp
+++ b/src/jit/lsraarmarch.cpp
@@ -46,6 +46,8 @@ int LinearScan::BuildIndir(GenTreeIndir* indirTree)
         return srcCount;
     }
 
+    bool isStore = (indirTree->gtOper == GT_STOREIND);
+
     GenTree* addr  = indirTree->Addr();
     GenTree* index = nullptr;
     int      cns   = 0;
diff --git a/src/jit/scopeinfo.cpp b/src/jit/scopeinfo.cpp
index 30189c82d2..9e8d6b911c 100644
--- a/src/jit/scopeinfo.cpp
+++ b/src/jit/scopeinfo.cpp
@@ -1326,6 +1326,7 @@ void CodeGen::psiBegProlog()
                     regNumber otherRegNum = REG_NA;
                     for (unsigned nCnt = 0; nCnt < structDesc.eightByteCount; nCnt++)
                     {
+                        unsigned  len     = structDesc.eightByteSizes[nCnt];
                         var_types regType = TYP_UNDEF;
 
                         if (nCnt == 0)
diff --git a/src/jit/simd.cpp b/src/jit/simd.cpp
index 6c6de0ea03..128118466c 100644
--- a/src/jit/simd.cpp
+++ b/src/jit/simd.cpp
@@ -2481,6 +2481,7 @@ GenTree* Compiler::impSIMDIntrinsic(OPCODE                opcode,
                 unsigned initCount    = argCount - 1;
                 unsigned elementCount = getSIMDVectorLength(size, baseType);
                 noway_assert(initCount == elementCount);
+                GenTree* nextArg = op2;
 
                 // Build a GT_LIST with the N values.
                 // We must maintain left-to-right order of the args, but we will pop
@@ -2489,6 +2490,7 @@ GenTree* Compiler::impSIMDIntrinsic(OPCODE                opcode,
                 GenTree* list              = nullptr;
                 GenTree* firstArg          = nullptr;
                 GenTree* prevArg           = nullptr;
+                int      offset            = 0;
                 bool     areArgsContiguous = true;
                 for (unsigned i = 0; i < initCount; i++)
                 {
@@ -2649,6 +2651,7 @@ GenTree* Compiler::impSIMDIntrinsic(OPCODE                opcode,
             assert(op2->TypeGet() == TYP_REF);
             GenTree* arrayRefForArgChk = op2;
             GenTree* argRngChk         = nullptr;
+            GenTree* asg               = nullptr;
             if ((arrayRefForArgChk->gtFlags & GTF_SIDE_EFFECT) != 0)
             {
                 op2 = fgInsertCommaFormTemp(&arrayRefForArgChk);
@@ -2753,6 +2756,7 @@ GenTree* Compiler::impSIMDIntrinsic(OPCODE                opcode,
             //    op2 - VSmall
             //    op1 - byref of VLarge
             assert(baseType == TYP_FLOAT);
+            unsigned elementByteCount = 4;
 
             GenTree* op4 = nullptr;
             if (argCount == 4)
diff --git a/src/jit/simdcodegenxarch.cpp b/src/jit/simdcodegenxarch.cpp
index 044183deb5..eb9c2b22e4 100644
--- a/src/jit/simdcodegenxarch.cpp
+++ b/src/jit/simdcodegenxarch.cpp
@@ -3079,6 +3079,7 @@ void CodeGen::genSIMDIntrinsicUpperRestore(GenTreeSIMD* simdNode)
     assert(op1->IsLocal() && op1->TypeGet() == TYP_SIMD32);
     regNumber srcReg    = simdNode->gtRegNum;
     regNumber lclVarReg = genConsumeReg(op1);
+    unsigned  varNum    = op1->AsLclVarCommon()->gtLclNum;
     assert(lclVarReg != REG_NA);
     assert(srcReg != REG_NA);
     if (simdNode->gtFlags & GTF_SPILLED)
diff --git a/src/jit/ssabuilder.cpp b/src/jit/ssabuilder.cpp
index 594e99dbe1..7fdc37ba93 100644
--- a/src/jit/ssabuilder.cpp
+++ b/src/jit/ssabuilder.cpp
@@ -1870,9 +1870,9 @@ void Compiler::JitTestCheckSSA()
     for (NodeToTestDataMap::KeyIterator ki = testData->Begin(); !ki.Equal(testData->End()); ++ki)
     {
         TestLabelAndNum tlAndN;
-        GenTree*        node       = ki.Get();
-        bool            nodeExists = testData->Lookup(node, &tlAndN);
-        assert(nodeExists);
+        GenTree*        node = ki.Get();
+        bool            b    = testData->Lookup(node, &tlAndN);
+        assert(b);
         if (tlAndN.m_tl == TL_SsaName)
         {
             if (node->OperGet() != GT_LCL_VAR)
@@ -1911,8 +1911,7 @@ void Compiler::JitTestCheckSSA()
                 }
                 // The mapping(s) must be one-to-one: if the label has a mapping, then the ssaNm must, as well.
                 ssize_t num2;
-                bool    ssaExists = ssaToLabel->Lookup(ssaNm, &num2);
-                assert(ssaExists);
+                bool    b = ssaToLabel->Lookup(ssaNm, &num2);
                 // And the mappings must be the same.
                 if (tlAndN.m_num != num2)
                 {
diff --git a/src/jit/valuenum.cpp b/src/jit/valuenum.cpp
index 4280d872b0..fb31d42667 100644
--- a/src/jit/valuenum.cpp
+++ b/src/jit/valuenum.cpp
@@ -5923,6 +5923,8 @@ void Compiler::fgValueNumberBlock(BasicBlock* blk)
     compCurStmtNum = blk->bbStmtNum - 1; // Set compCurStmtNum
 #endif
 
+    unsigned outerLoopNum = BasicBlock::NOT_IN_LOOP;
+
     // First: visit phi's.  If "newVNForPhis", give them new VN's.  If not,
     // first check to see if all phi args have the same value.
     GenTree* firstNonPhi = blk->FirstNonPhiDef();
@@ -7847,6 +7849,7 @@ void Compiler::fgValueNumberTree(GenTree* tree)
             // can recognize redundant loads with no stores between them.
             GenTree*             addr         = tree->AsIndir()->Addr();
             GenTreeLclVarCommon* lclVarTree   = nullptr;
+            FieldSeqNode*        fldSeq1      = nullptr;
             FieldSeqNode*        fldSeq2      = nullptr;
             GenTree*             obj          = nullptr;
             GenTree*             staticOffset = nullptr;
@@ -7888,6 +7891,9 @@ void Compiler::fgValueNumberTree(GenTree* tree)
                 ValueNum      inxVN  = ValueNumStore::NoVN;
                 FieldSeqNode* fldSeq = nullptr;
 
+                // GenTree* addr = tree->gtOp.gtOp1;
+                ValueNum addrVN = addrNvnp.GetLiberal();
+
                 // Try to parse it.
                 GenTree* arr = nullptr;
                 addr->ParseArrayAddress(this, &arrInfo, &arr, &inxVN, &fldSeq);
@@ -9743,8 +9749,7 @@ void Compiler::JitTestCheckVN()
                 }
                 // The mapping(s) must be one-to-one: if the label has a mapping, then the ssaNm must, as well.
                 ssize_t num2;
-                bool    found = vnToLabel->Lookup(vn, &num2);
-                assert(found);
+                bool    b = vnToLabel->Lookup(vn, &num2);
                 // And the mappings must be the same.
                 if (tlAndN.m_num != num2)
                 {