summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorHyung-Kyu Choi <hk0110.choi@samsung.com>2017-08-02 13:28:12 +0900
committerHyung-Kyu Choi <hk0110.choi@samsung.com>2017-08-02 13:28:12 +0900
commit578f6d338b5c3be20ee016b9e47ec55498ff9b84 (patch)
tree21d632b09989cfb27bda7549454b23dbc4c8c786
parentd91317e2d81fda173398c6575d991424a4bf05e2 (diff)
downloadcoreclr-578f6d338b5c3be20ee016b9e47ec55498ff9b84.tar.gz
coreclr-578f6d338b5c3be20ee016b9e47ec55498ff9b84.tar.bz2
coreclr-578f6d338b5c3be20ee016b9e47ec55498ff9b84.zip
Apply review feedback
- Use simpler condition and add an assertion - Fix typo Signed-off-by: Hyung-Kyu Choi <hk0110.choi@samsung.com>
-rw-r--r--src/jit/lsra.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/jit/lsra.cpp b/src/jit/lsra.cpp
index 0057076e6b..25b2af3351 100644
--- a/src/jit/lsra.cpp
+++ b/src/jit/lsra.cpp
@@ -5953,8 +5953,9 @@ regNumber LinearScan::allocateBusyReg(Interval* current, RefPosition* refPositio
RegRecord* physRegRecord2 = nullptr;
// For ARM32, let's consider two float registers consisting a double reg together,
// when allocaing a double register.
- if (current->registerType == TYP_DOUBLE && genIsValidDoubleReg(regNum))
+ if (current->registerType == TYP_DOUBLE)
{
+ assert(genIsValidDoubleReg(regNum));
physRegRecord2 = findAnotherHalfRegRec(physRegRecord);
}
#endif
@@ -6042,7 +6043,7 @@ regNumber LinearScan::allocateBusyReg(Interval* current, RefPosition* refPositio
RefPosition* recentAssignedRef = (assignedInterval == nullptr) ? nullptr : assignedInterval->recentRefPosition;
RefPosition* recentAssignedRef2 =
(assignedInterval2 == nullptr) ? nullptr : assignedInterval2->recentRefPosition;
- // There are four cases for ARM32 when we are trying to allocation a double register for TYP_DOUBLE
+ // There are four cases for ARM32 when we are trying to allocate a double register for TYP_DOUBLE
// Case 1: LoReg->assignedInterval != nullptr && HiReg->assignedInterval != nullptr
// Case 2: LoReg->assignedInterval != nullptr && HiReg->assignedInterval == nullptr
// Case 3: LoReg->assignedInterval == nullptr && HiReg->assignedInterval != nullptr