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AgeCommit message (Expand)AuthorFilesLines
2001-05-11Fix handling of XScale LDRD and STRD instructions with post indexed addressin...Nick Clifton1-0/+5
2001-05-08Check Mode not Bank in order to determine rocesor mode.Nick Clifton1-0/+5
2001-04-18* XScale coprocessor support.Matthew Green1-0/+41
2001-03-20Do not enable alignment checking when loading unaligned thumb instructions.Nick Clifton1-0/+5
2001-03-06Fix BLX(1) for ThumbNick Clifton1-0/+6
2001-02-28Add support for disabling alignment checks when performing GDB interfaceNick Clifton1-0/+30
2001-02-16Remove Prefetch abort for breakpoints. Instead set the state to RESUME.Nick Clifton1-0/+5
2001-02-15Add code to preserve processor mode when a prefetchNick Clifton1-0/+3
2001-02-14Reset processor into ARM mode for any machine type except the early ARMs.Nick Clifton1-0/+5
2001-02-14Prevent Aborts from happening whilst emulating a SWINick Clifton1-0/+7
2001-02-12Fix definition of NEGBRANCHNick Clifton1-0/+4
2001-02-01Update base address register after restoring register bank.Nick Clifton1-0/+7
2001-02-01Detect installation of SWI vector by running program as well as loading program.Nick Clifton1-0/+9
2000-12-19Fix test for StoreDouble Instruction.Nick Clifton1-0/+5
2000-12-11Add 0x91 as an FPE SWI.Nick Clifton1-0/+4
2000-12-08Add emulation of double word load and store instructions.Nick Clifton1-0/+8
2000-12-03Suppress support of DEMON swi's in XScale mode.Nick Clifton1-0/+6
2000-11-30Add support for ARM's v5TE architecture and Intel's XScale extenstionsNick Clifton1-1/+27
2000-09-15Replace StrongARM property with v4 and v5 properties.Nick Clifton1-0/+24
2000-08-15Compute write back value for post increment loads beforeNick Clifton1-0/+6
2000-07-142000-07-14 Fernando Nasser <fnasser@cygnus.com>Fernando Nasser1-0/+4
2000-07-142000-07-14 Fernando Nasser <fnasser@cygnus.com>Fernando Nasser1-0/+5
2000-07-04* armvirt.c (ABORTS): Do not define.Alexandre Oliva1-0/+2
2000-07-04* armdefs.h (struct ARMul_State): Add is_StrongARM.Alexandre Oliva1-0/+9
2000-07-04* armemu.c (ARMul_Emulate, t_undefined): Proceed to next insn.Alexandre Oliva1-0/+2
2000-07-04* armemu.h (INSN_SIZE): New macro.Alexandre Oliva1-0/+6
2000-07-04* armemu.c (LoadSMult): Use WriteR15() to discard the leastAlexandre Oliva1-0/+3
2000-07-04* armemu.h (WRITEDESTB): New macro.Alexandre Oliva1-0/+8
2000-07-04* armemu.h (GETSPSR): Call ARMul_GetSPSR().Alexandre Oliva1-0/+7
2000-07-04* armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New.Alexandre Oliva1-0/+8
2000-07-04* armemu.c (ARMul_Emulate): Compute writeback value beforeAlexandre Oliva1-0/+4
2000-07-04* armdefs.h (SYSTEMBANK): Define as USERBANK.Alexandre Oliva1-0/+5
2000-06-22* armemu.c (Multiply64): Fix computation of flag N.Alexandre Oliva1-0/+2
2000-06-22* armemu.c (MultiplyAdd64): Fix computation of flag N.Alexandre Oliva1-0/+4
2000-06-20* armemu.h (NEGBRANCH): Do not overwrite the two most significantAlexandre Oliva1-0/+5
2000-05-30Add support for v4 SystemMode.Nick Clifton1-1/+27
2000-05-24Change profiling so that it is enabled by default. Re-generate everything.Andrew Cagney1-0/+4
2000-05-23Add special case handling when GDB set CPSR registerNick Clifton1-0/+5
2000-04-10* arm abort fixFrank Ch. Eigler1-0/+5
2000-03-23* memory corruption fixFrank Ch. Eigler1-0/+4
2000-03-02* adding forgotten entryFrank Ch. Eigler1-0/+1
2000-02-08Fix compile time warning messages.Nick Clifton1-0/+11
2000-02-05import gdb-2000-02-04 snapshotJason Molenda1-0/+4
1999-12-07import gdb-1999-12-06 snapshotJason Molenda1-0/+7
1999-11-02import gdb-1999-11-01 snapshotJason Molenda1-0/+5
1999-10-12import gdb-1999-10-11 snapshotJason Molenda1-0/+6
1999-10-05import gdb-1999-10-04 snapshotJason Molenda1-0/+5
1999-09-09import gdb-1999-09-08 snapshotStan Shebs1-0/+4
1999-07-12import gdb-1999-07-12 snapshotJason Molenda1-0/+1
1999-05-11import gdb-1999-05-10Stan Shebs1-0/+4
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