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| author | Mike Frysinger <vapier@gentoo.org> | 2011-03-24 03:14:20 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-03-24 03:14:20 +0000 |
| commit | 8e670c0a3f7a40555a8ad85d350b896df4140825 (patch) | |
| tree | 25ac6049a4e2e6db4a51978f5b1f72ea09a52518 /sim | |
| parent | de0addfbefefa300907b90954f18f1e49f95e6bd (diff) | |
| download | binutils-8e670c0a3f7a40555a8ad85d350b896df4140825.tar.gz binutils-8e670c0a3f7a40555a8ad85d350b896df4140825.tar.bz2 binutils-8e670c0a3f7a40555a8ad85d350b896df4140825.zip | |
sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are set
The Blackfin PRM says that the top 8 bits of the accumulator must be
cleared when using the VIT_MAX insn, so the sim has followed this spec.
Matching the hardware behavior though when the high bits are not cleared
is easy to do and doesn't break existing behavior, so go for it.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/bfin/ChangeLog | 5 | ||||
| -rw-r--r-- | sim/bfin/bfin-sim.c | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog index 0e37dddc148..62d14bb4fc3 100644 --- a/sim/bfin/ChangeLog +++ b/sim/bfin/ChangeLog @@ -1,5 +1,10 @@ 2011-03-23 Robin Getz <robin.getz@analog.com> + * bfin-sim.c (decode_dsp32shift_0): Set acc0 to the unextended + value for the VIT_MAX insn, and mask off the result when done. + +2011-03-23 Robin Getz <robin.getz@analog.com> + * bfin-sim.c (decode_dsp32alu_0): Set A1 to a1_lo when up_hi is false, and set A0 to a0_lo when up_lo is false. diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c index 85e281a9d1d..467d7423070 100644 --- a/sim/bfin/bfin-sim.c +++ b/sim/bfin/bfin-sim.c @@ -5425,7 +5425,7 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) } else if ((sop == 0 || sop == 1) && sopcde == 9) { - bs40 acc0 = get_extended_acc (cpu, 0); + bs40 acc0 = get_unextended_acc (cpu, 0); bs16 sL, sH, out; TRACE_INSN (cpu, "R%i.L = VIT_MAX (R%i) (AS%c);", @@ -5435,7 +5435,7 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) sH = DREG (src1) >> 16; if (sop & 1) - acc0 >>= 1; + acc0 = (acc0 & 0xfeffffffffull) >> 1; else acc0 <<= 1; |