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| author | M R Swami Reddy <MR.Swami.Reddy@nsc.com> | 2008-04-08 09:07:02 +0000 |
|---|---|---|
| committer | M R Swami Reddy <MR.Swami.Reddy@nsc.com> | 2008-04-08 09:07:02 +0000 |
| commit | 49b964e71886819e4f8039c3c07fa20e8bd25760 (patch) | |
| tree | 2e443de89123c4ff62ea1bfacd010f455251afe0 /sim/testsuite | |
| parent | 51405f8781b67685ab1b058b8e7a9021b6ae6e31 (diff) | |
| download | binutils-49b964e71886819e4f8039c3c07fa20e8bd25760.tar.gz binutils-49b964e71886819e4f8039c3c07fa20e8bd25760.tar.bz2 binutils-49b964e71886819e4f8039c3c07fa20e8bd25760.zip | |
New files: Testcases for cr16 instruction set.
Diffstat (limited to 'sim/testsuite')
123 files changed, 2714 insertions, 0 deletions
diff --git a/sim/testsuite/sim/cr16/addb.cgs b/sim/testsuite/sim/cr16/addb.cgs new file mode 100644 index 00000000000..020f0fc52fb --- /dev/null +++ b/sim/testsuite/sim/cr16/addb.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for addb $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global add +add: + + movb $0x1234,r4 + movb $0x1234,r5 + addb r4, r5 + test_h_gr r5, 0x68 + + pass diff --git a/sim/testsuite/sim/cr16/addd.cgs b/sim/testsuite/sim/cr16/addd.cgs new file mode 100644 index 00000000000..cf9a9755fe2 --- /dev/null +++ b/sim/testsuite/sim/cr16/addd.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for addd $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global addd +addd: + + movd $0x12345678,(r4,r3) + addd $0x44444444,(r4,r3) + + test_h_grp "(r4,r3)", 0x56789abc + + pass diff --git a/sim/testsuite/sim/cr16/addi.cgs b/sim/testsuite/sim/cr16/addi.cgs new file mode 100644 index 00000000000..5d0fa1a14e8 --- /dev/null +++ b/sim/testsuite/sim/cr16/addi.cgs @@ -0,0 +1,30 @@ +# cr16 testcase for addi #$simm8, $dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global addi +addi: + + movb $1, r4 + addb $2, r4 + + cmpb $3,r4 + bne not_ok + + movw $0x1234, r5 + addw $0x1234, r5 + test_h_gr r5, 0x2468 + + pass + + movd $0x12345678, (r5,r4) + addd $0x12345678, (r5,r4) + test_h_grp "(r5,r4)", 0x2468acf0 + + pass + +not_ok: + fail diff --git a/sim/testsuite/sim/cr16/addw.cgs b/sim/testsuite/sim/cr16/addw.cgs new file mode 100644 index 00000000000..866349cb5fa --- /dev/null +++ b/sim/testsuite/sim/cr16/addw.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for addw $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global addw +addw: + + movw $0x1234,r4 + addw $0x1234,r4 + + test_h_gr r4, 0x2468 + + pass diff --git a/sim/testsuite/sim/cr16/andb.cgs b/sim/testsuite/sim/cr16/andb.cgs new file mode 100644 index 00000000000..56d10839ef2 --- /dev/null +++ b/sim/testsuite/sim/cr16/andb.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for and $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global and +and: + movb $3, r4 + movb $6, r5 + + andb r4,r5 + + test_h_gr r5, 2 + + pass diff --git a/sim/testsuite/sim/cr16/andd.cgs b/sim/testsuite/sim/cr16/andd.cgs new file mode 100644 index 00000000000..3951bf736fd --- /dev/null +++ b/sim/testsuite/sim/cr16/andd.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for and $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global and +and: + movd $0x33333333, (r4,r3) + movd $0x66666666, (r6,r5) + + andd (r4,r3), (r6,r5) + + test_h_grp "(r6,r5)", 0x22222222 + + pass diff --git a/sim/testsuite/sim/cr16/andw.cgs b/sim/testsuite/sim/cr16/andw.cgs new file mode 100644 index 00000000000..20bb3700576 --- /dev/null +++ b/sim/testsuite/sim/cr16/andw.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for and $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global and +and: + movw $3, r4 + movw $6, r5 + + andw r4, r5 + + test_h_gr r5, 2 + + pass diff --git a/sim/testsuite/sim/cr16/ashub.cgs b/sim/testsuite/sim/cr16/ashub.cgs new file mode 100644 index 00000000000..b3113e1535b --- /dev/null +++ b/sim/testsuite/sim/cr16/ashub.cgs @@ -0,0 +1,26 @@ +# cr16 testcase for ashub $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ashub +ashub: + + movw $0x12f1, r4 + movw $4,r5 + ashub r5, r4 + + cmpw $0x1210, r4 + beq ok +not_ok: + fail +ok: + movw $0x12f1, r4 + movw $-4,r5 + ashub r5, r4 + + test_h_gr r4, 0x12ff + + pass diff --git a/sim/testsuite/sim/cr16/ashub_i.cgs b/sim/testsuite/sim/cr16/ashub_i.cgs new file mode 100644 index 00000000000..ce0af1d6f59 --- /dev/null +++ b/sim/testsuite/sim/cr16/ashub_i.cgs @@ -0,0 +1,24 @@ +# cr16 testcase for ashub $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ashub +ashub: + + movw $0x12f1, r4 + ashub $4, r4 + + cmpw $0x1210, r4 + beq ok +not_ok: + fail +ok: + movw $0x12f1, r4 + ashub $-4, r4 + + test_h_gr r4, 0x12ff + + pass diff --git a/sim/testsuite/sim/cr16/ashud.cgs b/sim/testsuite/sim/cr16/ashud.cgs new file mode 100644 index 00000000000..91b6e754bb4 --- /dev/null +++ b/sim/testsuite/sim/cr16/ashud.cgs @@ -0,0 +1,26 @@ +# cr16 testcase for ashud $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ashud +ashud: + + movd $0xf1234567, (r4,r3) + movw $20,r5 + ashud r5, (r4,r3) + + cmpd $0x56700000, (r4,r3) + beq ok +not_ok: + fail +ok: + movd $0xf1234567, (r4,r3) + movw $-20,r5 + ashud r5, (r4,r3) + + test_h_grp "(r4,r3)", -238 + + pass diff --git a/sim/testsuite/sim/cr16/ashud_i.cgs b/sim/testsuite/sim/cr16/ashud_i.cgs new file mode 100644 index 00000000000..3b457972d8b --- /dev/null +++ b/sim/testsuite/sim/cr16/ashud_i.cgs @@ -0,0 +1,24 @@ +# cr16 testcase for ashud $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ashud +ashud: + + movd $0xf1234567, (r4,r3) + ashud $20, (r4,r3) + + cmpd $0x56700000, (r4,r3) + beq ok +not_ok: + fail +ok: + movd $0xf1234567, (r4,r3) + ashud $-20, (r4,r3) + + test_h_grp "(r4,r3)", -238 + + pass diff --git a/sim/testsuite/sim/cr16/ashuw.cgs b/sim/testsuite/sim/cr16/ashuw.cgs new file mode 100644 index 00000000000..8ef3cf721fc --- /dev/null +++ b/sim/testsuite/sim/cr16/ashuw.cgs @@ -0,0 +1,26 @@ +# cr16 testcase for ashuw $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ashuw +ashuw: + + movw $0x1ff1, r4 + movw $12,r5 + ashuw r5, r4 + + cmpw $0x1000, r4 + beq ok +not_ok: + fail +ok: + movw $0x1ff1, r4 + movw $-12,r5 + ashuw r5, r4 + + test_h_gr r4, 0x1 + + pass diff --git a/sim/testsuite/sim/cr16/ashuw_i.cgs b/sim/testsuite/sim/cr16/ashuw_i.cgs new file mode 100644 index 00000000000..0a8322a2304 --- /dev/null +++ b/sim/testsuite/sim/cr16/ashuw_i.cgs @@ -0,0 +1,24 @@ +# cr16 testcase for ashuw $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ashuw +ashuw: + + movw $0x1ff1, r4 + ashuw $12, r4 + + cmpw $0x1000, r4 + beq ok +not_ok: + fail +ok: + movw $0x1ff1, r4 + ashuw $-12, r4 + + test_h_gr r4, 0x1 + + pass diff --git a/sim/testsuite/sim/cr16/bal1_24.cgs b/sim/testsuite/sim/cr16/bal1_24.cgs new file mode 100644 index 00000000000..a174b31a9f4 --- /dev/null +++ b/sim/testsuite/sim/cr16/bal1_24.cgs @@ -0,0 +1,15 @@ +# cr16 testcase for bal $disp24 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global bal24 +bal24: + bal (ra), ok + + fail + +ok: + pass diff --git a/sim/testsuite/sim/cr16/bal2_24.cgs b/sim/testsuite/sim/cr16/bal2_24.cgs new file mode 100644 index 00000000000..37cda7f08da --- /dev/null +++ b/sim/testsuite/sim/cr16/bal2_24.cgs @@ -0,0 +1,15 @@ +# cr16 testcase for bal $disp24 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global bal24 +bal24: + bal (r12), ok + + fail + +ok: + pass diff --git a/sim/testsuite/sim/cr16/bcc.cgs b/sim/testsuite/sim/cr16/bcc.cgs new file mode 100644 index 00000000000..b0bee2b455d --- /dev/null +++ b/sim/testsuite/sim/cr16/bcc.cgs @@ -0,0 +1,22 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $12, r4 + movw $10, r5 + cmpw r4, r5 + bcc ok +not_ok: + fail +ok: + movw $11, r5 + cmpw r4, r5 + beq not_ok + + pass diff --git a/sim/testsuite/sim/cr16/bcs.cgs b/sim/testsuite/sim/cr16/bcs.cgs new file mode 100644 index 00000000000..0ba14b15c05 --- /dev/null +++ b/sim/testsuite/sim/cr16/bcs.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for bcs disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global bcs +bcs: + mvi_h_condbit 0 + movw $12, r4 + movw $10, r5 + subw r4, r5 + bcs ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/beq.cgs b/sim/testsuite/sim/cr16/beq.cgs new file mode 100644 index 00000000000..35ece277ccf --- /dev/null +++ b/sim/testsuite/sim/cr16/beq.cgs @@ -0,0 +1,22 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $12, r4 + movw $12, r5 + cmpw r4, r5 + beq ok +not_ok: + fail +ok: + movw $11, r5 + cmpw r4, r5 + beq not_ok + + pass diff --git a/sim/testsuite/sim/cr16/beq0b.cgs b/sim/testsuite/sim/cr16/beq0b.cgs new file mode 100644 index 00000000000..af6a26b5253 --- /dev/null +++ b/sim/testsuite/sim/cr16/beq0b.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for beq0b reg disp5 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq0b +beq0b: + mvi_h_condbit 0 + movw $0x1200, r4 + beq0b r4, 0x1a +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/beq0w.cgs b/sim/testsuite/sim/cr16/beq0w.cgs new file mode 100644 index 00000000000..b3805acc974 --- /dev/null +++ b/sim/testsuite/sim/cr16/beq0w.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $0, r4 + beq0b r4, 0x1a +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/bge.cgs b/sim/testsuite/sim/cr16/bge.cgs new file mode 100644 index 00000000000..bb705e7df33 --- /dev/null +++ b/sim/testsuite/sim/cr16/bge.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + bgt ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/bgt.cgs b/sim/testsuite/sim/cr16/bgt.cgs new file mode 100644 index 00000000000..bb705e7df33 --- /dev/null +++ b/sim/testsuite/sim/cr16/bgt.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + bgt ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/bhi.cgs b/sim/testsuite/sim/cr16/bhi.cgs new file mode 100644 index 00000000000..9a88af723ef --- /dev/null +++ b/sim/testsuite/sim/cr16/bhi.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + bhi ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/bhs.cgs b/sim/testsuite/sim/cr16/bhs.cgs new file mode 100644 index 00000000000..97dcc55c5d7 --- /dev/null +++ b/sim/testsuite/sim/cr16/bhs.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for bhi disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global bhi +bhi: + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + bhs ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/bht.cgs b/sim/testsuite/sim/cr16/bht.cgs new file mode 100644 index 00000000000..39912e22da4 --- /dev/null +++ b/sim/testsuite/sim/cr16/bht.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + blt ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/blo.cgs b/sim/testsuite/sim/cr16/blo.cgs new file mode 100644 index 00000000000..39912e22da4 --- /dev/null +++ b/sim/testsuite/sim/cr16/blo.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + blt ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/bls.cgs b/sim/testsuite/sim/cr16/bls.cgs new file mode 100644 index 00000000000..f3945703902 --- /dev/null +++ b/sim/testsuite/sim/cr16/bls.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + bls ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/blt.cgs b/sim/testsuite/sim/cr16/blt.cgs new file mode 100644 index 00000000000..39912e22da4 --- /dev/null +++ b/sim/testsuite/sim/cr16/blt.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + blt ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/bnc24.cgs b/sim/testsuite/sim/cr16/bnc24.cgs new file mode 100644 index 00000000000..f060d298627 --- /dev/null +++ b/sim/testsuite/sim/cr16/bnc24.cgs @@ -0,0 +1,20 @@ +# cr16 testcase for bnc $disp24 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global bnc24 +bnc24: + mvi_h_condbit 0 + bnc.l test0pass + +test1fail: + fail +test0pass: + + mvi_h_condbit 1 + bnc.l test1fail + + pass diff --git a/sim/testsuite/sim/cr16/bnc8.cgs b/sim/testsuite/sim/cr16/bnc8.cgs new file mode 100644 index 00000000000..b3faec4e2ee --- /dev/null +++ b/sim/testsuite/sim/cr16/bnc8.cgs @@ -0,0 +1,20 @@ +# cr16 testcase for bnc $disp8 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global bnc8 +bnc8: + mvi_h_condbit 0 + bnc.s test0pass + +test1fail: + fail + +test0pass: + mvi_h_condbit 1 + bnc.s test1fail + + pass diff --git a/sim/testsuite/sim/cr16/bne.cgs b/sim/testsuite/sim/cr16/bne.cgs new file mode 100644 index 00000000000..3740f2463ec --- /dev/null +++ b/sim/testsuite/sim/cr16/bne.cgs @@ -0,0 +1,22 @@ +# cr16 testcase for bne disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global bne +bne: + movw $1, r4 + movw $2, r5 + cmpw r4,r5 + bne test0pass +test1fail: + fail + +test0pass: + movw $1, r5 + cmpw r4,r5 + bne test1fail + + pass diff --git a/sim/testsuite/sim/cr16/bne0b.cgs b/sim/testsuite/sim/cr16/bne0b.cgs new file mode 100644 index 00000000000..63f3cadd7d7 --- /dev/null +++ b/sim/testsuite/sim/cr16/bne0b.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for bne0b reg disp5 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ne0b +bne0b: + mvi_h_condbit 0 + movw $0x1201, r4 + bne0b r4, 0x1a +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/bne0w.cgs b/sim/testsuite/sim/cr16/bne0w.cgs new file mode 100644 index 00000000000..f45e39905e7 --- /dev/null +++ b/sim/testsuite/sim/cr16/bne0w.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for bne0w reg disp5 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global bne0w +bne0w: + mvi_h_condbit 0 + movw $1, r4 + bne0w r4, 0x1a +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/br.cgs b/sim/testsuite/sim/cr16/br.cgs new file mode 100644 index 00000000000..f7ba86dde37 --- /dev/null +++ b/sim/testsuite/sim/cr16/br.cgs @@ -0,0 +1,24 @@ +# cr16 testcase for bc $disp24 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global bc24 +bc24: + + mvi_h_condbit 0 + bne test0fail + br test0pass +test0fail: + fail +test0pass: + + mvi_h_condbit 1 + bne test1pass + fail +test1pass: + + pass + diff --git a/sim/testsuite/sim/cr16/cmpb.cgs b/sim/testsuite/sim/cr16/cmpb.cgs new file mode 100644 index 00000000000..50984bf8ef5 --- /dev/null +++ b/sim/testsuite/sim/cr16/cmpb.cgs @@ -0,0 +1,23 @@ +# cr16 testcase for cmpb reg1, reg2 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global cmpb +cmpb: + mvi_h_condbit 0 + movw $0x2311, r4 + movw $0x4211, r5 + cmpb r4,r5 + beq ok +not_ok: + fail +ok: + mvi_h_condbit 1 + movw $0x4222, r5 + cmpb r4,r5 + beq not_ok + + pass diff --git a/sim/testsuite/sim/cr16/cmpb_i.cgs b/sim/testsuite/sim/cr16/cmpb_i.cgs new file mode 100644 index 00000000000..591abe9a849 --- /dev/null +++ b/sim/testsuite/sim/cr16/cmpb_i.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for cmpb $imm4, reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global cmpb_i +cmpb_i: + mvi_h_condbit 0 + movw $0x2311, r4 + cmpb $0x4211, r4 + beq ok +not_ok: + fail +ok: + mvi_h_condbit 1 + cmpb $0x4222,r4 + beq not_ok + + pass diff --git a/sim/testsuite/sim/cr16/cmpd.cgs b/sim/testsuite/sim/cr16/cmpd.cgs new file mode 100644 index 00000000000..cc9e55ddb6c --- /dev/null +++ b/sim/testsuite/sim/cr16/cmpd.cgs @@ -0,0 +1,23 @@ +# cr16 testcase for cmpd (regp), (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global cmpd +cmpd: + mvi_h_condbit 0 + movd $0x12345678, (r4,r3) + movd $0x12345678, (r6,r5) + cmpd (r4,r3), (r6,r5) + beq ok +not_ok: + fail +ok: + mvi_h_condbit 1 + movd $0x12341234, (r6,r5) + cmpd (r4,r3), (r6,r5) + beq not_ok + + pass diff --git a/sim/testsuite/sim/cr16/cmpd_i.cgs b/sim/testsuite/sim/cr16/cmpd_i.cgs new file mode 100644 index 00000000000..ad6018ad362 --- /dev/null +++ b/sim/testsuite/sim/cr16/cmpd_i.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for cmpb $imm32,(regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global cmpd_i +cmpd_i: + mvi_h_condbit 0 + movd $0x12345678, (r4,r3) + cmpd $0x12345678, (r4,r3) + beq ok +not_ok: + fail +ok: + mvi_h_condbit 1 + cmpd $0x12341234, (r4,r3) + beq not_ok + + pass diff --git a/sim/testsuite/sim/cr16/cmpi.cgs b/sim/testsuite/sim/cr16/cmpi.cgs new file mode 100644 index 00000000000..e7302b874dd --- /dev/null +++ b/sim/testsuite/sim/cr16/cmpi.cgs @@ -0,0 +1,23 @@ +# cr16 testcase for cmpi $src2,#$simm16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global cmpi +cmpi: + mvi_h_condbit 0 + movw $1, r4 + cmpw $1, r4 + beq ok +not_ok: + fail +ok: + mvi_h_condbit 1 + movw $2, r4 + cmpw $2, r4 + bne not_ok + + + pass diff --git a/sim/testsuite/sim/cr16/cmpw.cgs b/sim/testsuite/sim/cr16/cmpw.cgs new file mode 100644 index 00000000000..5570a108bd3 --- /dev/null +++ b/sim/testsuite/sim/cr16/cmpw.cgs @@ -0,0 +1,23 @@ +# cr16 testcase for cmp $src1,$src2 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global cmp +cmp: + mvi_h_condbit 0 + movw $0x1234, r4 + movw $0x1234, r5 + cmpb r4,r5 + beq ok +not_ok: + fail +ok: + mvi_h_condbit 1 + movw $0x2222, r5 + cmpw r4,r5 + beq not_ok + + pass diff --git a/sim/testsuite/sim/cr16/cmpw_i.cgs b/sim/testsuite/sim/cr16/cmpw_i.cgs new file mode 100644 index 00000000000..31f701c5171 --- /dev/null +++ b/sim/testsuite/sim/cr16/cmpw_i.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for cmpw_i $imm16, reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global cmpw_i +cmpw_i: + mvi_h_condbit 0 + movw $0x1234, r4 + cmpw $0x1234, r4 + beq ok +not_ok: + fail +ok: + mvi_h_condbit 1 + cmpw $0x2222, r4 + beq not_ok + + pass diff --git a/sim/testsuite/sim/cr16/excp.cgs b/sim/testsuite/sim/cr16/excp.cgs new file mode 100644 index 00000000000..82d445a5d4c --- /dev/null +++ b/sim/testsuite/sim/cr16/excp.cgs @@ -0,0 +1,110 @@ +# cr16 testcase for excp uimm4 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global excp +excp: + pass # pass macro use the excp 8 + +## Test 1: bbpsw = 0, bpsw = 1, psw = 0 +# +# # bbsm = 0, bie = 0, bbcond = 0 +# movw $0, r4 +# lpr r4, cr8 +# +# # bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 +# movw $0xc100, r4 +# lpr r4, cr0 +# +# # bbpc = 0 +# movw $0, r4 +# mvtc r4, bbpc +# +# # bpc = 42 +# mvaddr_h_gr r4, 42 +# mvtc r4, bpc +# +# # Copy excp2_handler to excp area of memory. +# ld24 r0,#0x48 # address of excp 2 handler +# ld24 r1,#excp2_handler +# ld r2,@r1 +# st r2,@r0 +# # Set up return address. +# ld24 r5,#excp2_ret1 +# +#excp_insn1: +# excp 2 +# fail +# +#excp2_ret1: +# # test bbsm = 1, bbie = 1, bbcond = 1 +# mvfc r4, cr8 +# test_h_gr r4, 0xc1 +# +# # test bsm = 0, bie = 0, bcond = 0, sm = 0, ie = 0, cond = 0 +# mvfc r4, cr0 +# test_h_gr r4, 0 +# +# # test bbpc = 42 +# mvfc r4, bbpc +# test_h_gr r4, 42 +# +# # test bpc = proper return address +# mvfc r4, bpc +# test_h_gr r4, excp_insn1 + 4 +# +## Test 2: bbpsw = 1, bpsw = 0, psw = 1 +# +# # bbsm = 1, bie = 1, bbcond = 1 +# mvi_h_gr r4, 0xc1 +# mvtc r4, cr8 +# +# # bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 +# mvi_h_gr r4, 0xc1 +# mvtc r4, cr0 +# +# # bbpc = 42 +# mvaddr_h_gr r4, 42 +# mvtc r4, bbpc +# +# # bpc = 0 +# mvaddr_h_gr r4, 0 +# mvtc r4, bpc +# +# # Set up return address. +# ld24 r5,#excp2_ret2 +# +#excp_insn2: +# excp #2 +# fail +# +#excp2_ret2: +# # test bbsm = 0, bbie = 0, bbcond = 0 +# mvfc r4, cr8 +# test_h_gr r4, 0 +# +# # test bsm = 1, bie = 1, bcond = 1, sm = 1, ie = 0, cond = 0 +# mvfc r4, cr0 +# test_h_gr r4, 0xc180 +# +# # test bbpc = 0 +# mvfc r4, bbpc +# test_h_gr r4, 0 +# +# # test bpc = proper return address +# mvfc r4, bpc +# test_h_gr r4, excp_insn2 + 4 +# +# pass +# +# .data +# +## Don't use rte as it will undo the effects of excp we're testing. +# +# .p2align 2 +#excp2_handler: +# jmp r5 +# nop diff --git a/sim/testsuite/sim/cr16/hello.ms b/sim/testsuite/sim/cr16/hello.ms new file mode 100644 index 00000000000..ab6c4824779 --- /dev/null +++ b/sim/testsuite/sim/cr16/hello.ms @@ -0,0 +1,19 @@ +# output(): Hello world!\n +# mach(): cr16 + + .globl _start +_start: + +# write (hello world) + movw $1,r2 + movd $hello,(r4,r3) + loadw length,r5 + movw $0x404,r0 + excp 8 +# exit (0) + movw $0,r2 + movw $0x410,r0 + excp 8 + +length: .long 14 +hello: .ascii "Hello world!\r\n" diff --git a/sim/testsuite/sim/cr16/jal.cgs b/sim/testsuite/sim/cr16/jal.cgs new file mode 100644 index 00000000000..106c8649dc3 --- /dev/null +++ b/sim/testsuite/sim/cr16/jal.cgs @@ -0,0 +1,35 @@ +# cr16 testcase for jal $sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jal +jal: + movd $ok1, (r5, r4) + lshd $-1, (r5,r4) + jal (ra), (r5,r4) +not_ok: + fail +ok1: + movd $not_ok, (r7, r6) + lshd $-1, (r7,r6) + cmpd (r7,r6), (ra) + beq ok2 + br not_ok +ok2: + movd $ok3, (r5, r4) + lshd $-1, (r5,r4) + jal (r1,r0), (r5,r4) +not_ok1: + br not_ok +ok3: + movd $not_ok1, (r7, r6) + lshd $-1, (r7,r6) + cmpd (r7,r6), (r1,r0) + beq ok4 + br not_ok +ok4: + + pass diff --git a/sim/testsuite/sim/cr16/jcc.cgs b/sim/testsuite/sim/cr16/jcc.cgs new file mode 100644 index 00000000000..84db77a4bc5 --- /dev/null +++ b/sim/testsuite/sim/cr16/jcc.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jcc (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jcc +jcc: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $12, r4 + movw $10, r5 + cmpw r4, r5 + jcc (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/jcs.cgs b/sim/testsuite/sim/cr16/jcs.cgs new file mode 100644 index 00000000000..91d40a3dc06 --- /dev/null +++ b/sim/testsuite/sim/cr16/jcs.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jcs (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jcs +jcs: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $12, r4 + movw $10, r5 + subw r4, r5 + jcs (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/jeq.cgs b/sim/testsuite/sim/cr16/jeq.cgs new file mode 100644 index 00000000000..824828d2692 --- /dev/null +++ b/sim/testsuite/sim/cr16/jeq.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jeq (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jeq +jeq: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $12, r4 + movw $12, r5 + cmpw r4, r5 + jeq (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/jfc.cgs b/sim/testsuite/sim/cr16/jfc.cgs new file mode 100644 index 00000000000..0bf1c298c7e --- /dev/null +++ b/sim/testsuite/sim/cr16/jfc.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jfc (repl) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jfc +jfc: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + subw r4, r5 + jfc (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/jfs.cgs b/sim/testsuite/sim/cr16/jfs.cgs new file mode 100644 index 00000000000..c14f5651e28 --- /dev/null +++ b/sim/testsuite/sim/cr16/jfs.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jfs (repl) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jfs +jfs: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $0xaa, r4 + movw $0xaa, r5 + addb r4, r5 + jfs (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/jge.cgs b/sim/testsuite/sim/cr16/jge.cgs new file mode 100644 index 00000000000..685ba4c42dd --- /dev/null +++ b/sim/testsuite/sim/cr16/jge.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jge (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jge +jge: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + jge (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/jgt.cgs b/sim/testsuite/sim/cr16/jgt.cgs new file mode 100644 index 00000000000..e1bed75b0a6 --- /dev/null +++ b/sim/testsuite/sim/cr16/jgt.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jgt (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jgt +jgt: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + jgt (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/jhi.cgs b/sim/testsuite/sim/cr16/jhi.cgs new file mode 100644 index 00000000000..0959d1df0f5 --- /dev/null +++ b/sim/testsuite/sim/cr16/jhi.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jeq (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jeq +jeq: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + jhi (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/jhs.cgs b/sim/testsuite/sim/cr16/jhs.cgs new file mode 100644 index 00000000000..80a39441c31 --- /dev/null +++ b/sim/testsuite/sim/cr16/jhs.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jhs (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jhs +jhs: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + subw r4, r5 + jhs (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/jlo.cgs b/sim/testsuite/sim/cr16/jlo.cgs new file mode 100644 index 00000000000..cf00e3ed186 --- /dev/null +++ b/sim/testsuite/sim/cr16/jlo.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jlo (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jlo +jlo: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + jlo (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/jls.cgs b/sim/testsuite/sim/cr16/jls.cgs new file mode 100644 index 00000000000..be50f74bae7 --- /dev/null +++ b/sim/testsuite/sim/cr16/jls.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jeq (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jeq +jeq: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + jls (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/jlt.cgs b/sim/testsuite/sim/cr16/jlt.cgs new file mode 100644 index 00000000000..99c18626cbf --- /dev/null +++ b/sim/testsuite/sim/cr16/jlt.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jlt (repl) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jlt +jlt: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + jlt (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/jne.cgs b/sim/testsuite/sim/cr16/jne.cgs new file mode 100644 index 00000000000..fb868890b8a --- /dev/null +++ b/sim/testsuite/sim/cr16/jne.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jne (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jne +jne: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $0, r4 + movw $1, r5 + cmpw r4, r5 + jne (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/jump.cgs b/sim/testsuite/sim/cr16/jump.cgs new file mode 100644 index 00000000000..b2b4774880f --- /dev/null +++ b/sim/testsuite/sim/cr16/jump.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for jmp $sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jmp +jmp: + movd $ok1, (r4,r3) + jump (r4,r3) + fail +ok1: + movd $ok2, (r4,r3) + jump (r4,r3) + fail +ok2: + pass diff --git a/sim/testsuite/sim/cr16/loadb.cgs b/sim/testsuite/sim/cr16/loadb.cgs new file mode 100644 index 00000000000..c591ec9acea --- /dev/null +++ b/sim/testsuite/sim/cr16/loadb.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for loadb $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ldb +ldb: + movd $data_loc, (r4,r3) + movw $0,r5 + + loadb 0(r4,r3),r5 + + test_h_gr r5, 0x78 # little endian processor + + pass + +data_loc: + .word 0x5678 + diff --git a/sim/testsuite/sim/cr16/loadd.cgs b/sim/testsuite/sim/cr16/loadd.cgs new file mode 100644 index 00000000000..03306876a7d --- /dev/null +++ b/sim/testsuite/sim/cr16/loadd.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for ldb $dr,@$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ldb +ldb: + movd $data_loc, (r4,r3) + movd $0,(r6,r5) + + loadd 0(r4,r3),(r6,r5) + + test_h_grp "(r6, r5)", 0x12345678 # little endian processor + + pass + +data_loc: + .long 0x12345678 + diff --git a/sim/testsuite/sim/cr16/loadm.cgs b/sim/testsuite/sim/cr16/loadm.cgs new file mode 100644 index 00000000000..8bd6d11f727 --- /dev/null +++ b/sim/testsuite/sim/cr16/loadm.cgs @@ -0,0 +1,41 @@ +# cr16 testcase for loadm count +# mach(): cr16 + + .include "testutils.inc" + + start + + .global loadm +loadm: + movw $0x1000, r0 + movw $0x12, r2 + storw r2, 0x1000 + movw $0x34, r3 + storw r3, 0x1002 + movw $0x56, r4 + storw r4, 0x1004 + movw $0x78, r5 + storw r5, 0x1006 + + loadm $4 + + cmpw $0x12,r2 + beq ok1 +not_ok: + fail +ok1: + cmpw $0x34,r3 + beq ok2 + br not_ok +ok2: + cmpw $0x56,r4 + beq ok3 + br not_ok +ok3: + cmpw $0x78,r5 + beq ok4 + br not_ok +ok4: + pass + pass + diff --git a/sim/testsuite/sim/cr16/loadmp.cgs b/sim/testsuite/sim/cr16/loadmp.cgs new file mode 100644 index 00000000000..6003c3f5128 --- /dev/null +++ b/sim/testsuite/sim/cr16/loadmp.cgs @@ -0,0 +1,40 @@ +# cr16 testcase for loadmp count +# mach(): cr16 + + .include "testutils.inc" + + start + + .global loadmp +loadmp: + movd $0x1000, (r1,r0) + movw $0x12, r2 + storw r2, 0x1000 + movw $0x34, r3 + storw r3, 0x1002 + movw $0x56, r4 + storw r4, 0x1004 + movw $0x78, r5 + storw r5, 0x1006 + + loadmp $4 + + cmpw $0x12,r2 + beq ok1 +not_ok: + fail +ok1: + cmpw $0x34,r3 + beq ok2 + br not_ok +ok2: + cmpw $0x56,r4 + beq ok3 + br not_ok +ok3: + cmpw $0x78,r5 + beq ok4 + br not_ok +ok4: + pass + diff --git a/sim/testsuite/sim/cr16/loadw.cgs b/sim/testsuite/sim/cr16/loadw.cgs new file mode 100644 index 00000000000..47d92ad4663 --- /dev/null +++ b/sim/testsuite/sim/cr16/loadw.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for ldb $dr,@$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ldb +ldb: + movd $data_loc, (r4,r3) + movw $0,r5 + + loadw 0(r4,r3),r5 + + test_h_gr r5, 0x5678 # little endian processor + + pass + +data_loc: + .word 0x5678 + diff --git a/sim/testsuite/sim/cr16/lpr-spr.cgs b/sim/testsuite/sim/cr16/lpr-spr.cgs new file mode 100644 index 00000000000..c2679eaca7a --- /dev/null +++ b/sim/testsuite/sim/cr16/lpr-spr.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for lpr reg, preg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global lpr +lpr: + movw $0x1234,r3 + lpr r3, psr + + spr psr,r5 + + + test_h_gr r5, 0x1234 + + pass diff --git a/sim/testsuite/sim/cr16/lprd-sprd.cgs b/sim/testsuite/sim/cr16/lprd-sprd.cgs new file mode 100644 index 00000000000..3df8de36a63 --- /dev/null +++ b/sim/testsuite/sim/cr16/lprd-sprd.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for lprd reg, preg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global lprd +lprd: + movd $0x12345678,(r4,r3) + lprd (r4,r3), psr + + sprd psr,(r6,r5) + + + test_h_grp "(r6,r5)", 0x12345678 + + pass diff --git a/sim/testsuite/sim/cr16/lshb.cgs b/sim/testsuite/sim/cr16/lshb.cgs new file mode 100644 index 00000000000..877f33f51a6 --- /dev/null +++ b/sim/testsuite/sim/cr16/lshb.cgs @@ -0,0 +1,15 @@ +# cr16 testcase for sll $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global sll +sll: + movb $6, r4 + movb $1, r5 + lshb r5, r4 + test_h_gr r4, 12 + + pass diff --git a/sim/testsuite/sim/cr16/lshb_i.cgs b/sim/testsuite/sim/cr16/lshb_i.cgs new file mode 100644 index 00000000000..5302183f21e --- /dev/null +++ b/sim/testsuite/sim/cr16/lshb_i.cgs @@ -0,0 +1,14 @@ +# cr16 testcase for lshb_i $dr,#$uimm5 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global lshb_i +lshb_i: + movb $6,r4 + lshb $1, r4 + test_h_gr r4, 12 + + pass diff --git a/sim/testsuite/sim/cr16/lshd.cgs b/sim/testsuite/sim/cr16/lshd.cgs new file mode 100644 index 00000000000..d4554071f07 --- /dev/null +++ b/sim/testsuite/sim/cr16/lshd.cgs @@ -0,0 +1,15 @@ +# cr16 testcase for sll $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global sll +sll: + movd $0x12345678, (r4,r3) + movw $0x10, r5 + lshd r5, (r4,r3) + test_h_grp "(r4,r3)", 0x56780000 + + pass diff --git a/sim/testsuite/sim/cr16/lshd_i.cgs b/sim/testsuite/sim/cr16/lshd_i.cgs new file mode 100644 index 00000000000..b517f38efab --- /dev/null +++ b/sim/testsuite/sim/cr16/lshd_i.cgs @@ -0,0 +1,14 @@ +# cr16 testcase for lshb_i $dr,#$uimm5 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global lshb_i +lshb_i: + movd $0x12345678,(r4,r3) + lshd $16, (r4,r3) + test_h_grp "(r4,r3)", 0x56780000 + + pass diff --git a/sim/testsuite/sim/cr16/lshw.cgs b/sim/testsuite/sim/cr16/lshw.cgs new file mode 100644 index 00000000000..536fe2f3a21 --- /dev/null +++ b/sim/testsuite/sim/cr16/lshw.cgs @@ -0,0 +1,15 @@ +# cr16 testcase for sll $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global sll +sll: + movw $0x1234, r4 + movw $8, r5 + lshw r5, r4 + test_h_gr r4, 0x3400 + + pass diff --git a/sim/testsuite/sim/cr16/lshw_i.cgs b/sim/testsuite/sim/cr16/lshw_i.cgs new file mode 100644 index 00000000000..c559f49fd57 --- /dev/null +++ b/sim/testsuite/sim/cr16/lshw_i.cgs @@ -0,0 +1,14 @@ +# cr16 testcase for lshb_i $dr,#$uimm5 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global lshb_i +lshb_i: + movw $0x1234,r4 + lshw $8, r4 + test_h_gr r4, 0x3400 + + pass diff --git a/sim/testsuite/sim/cr16/macqw.cgs b/sim/testsuite/sim/cr16/macqw.cgs new file mode 100644 index 00000000000..4c6da4fcaf4 --- /dev/null +++ b/sim/testsuite/sim/cr16/macqw.cgs @@ -0,0 +1,15 @@ +# cr16 testcase for macqw reg, (regp) +# mach(): cr16 + + .include "testutils.inc" + + start # REVIST to update testcase + + .global macqw +macqw: + movw $0x123,r3 + movw $0x456,r4 + macqw r3, r4, (r6,r5) + test_h_grp "(r6,r5)", 0x4edc2 + + pass diff --git a/sim/testsuite/sim/cr16/macsw.cgs b/sim/testsuite/sim/cr16/macsw.cgs new file mode 100644 index 00000000000..8a0f22747d3 --- /dev/null +++ b/sim/testsuite/sim/cr16/macsw.cgs @@ -0,0 +1,15 @@ +# cr16 testcase for macsw reg, (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global macsw # REVISIT to update this testcase +macsw: + movw $0x123,r3 + movw $0x456,r4 + macsw r3,r4, (r6,r5) + test_h_grp "(r6,r5)", 0x4edc2 + + pass diff --git a/sim/testsuite/sim/cr16/macuw.cgs b/sim/testsuite/sim/cr16/macuw.cgs new file mode 100644 index 00000000000..ea4c3fc4d39 --- /dev/null +++ b/sim/testsuite/sim/cr16/macuw.cgs @@ -0,0 +1,15 @@ +# cr16 testcase for macuw reg, reg, (regp) +# mach(): cr16 + + .include "testutils.inc" + + start # REVIST to update testcase + + .global macuw +macuw: + movw $0x123,r3 + movw $0x456,r4 + macuw r3, r4, (r6,r5) + test_h_grp "(r6,r5)", 0x4edc2 + + pass diff --git a/sim/testsuite/sim/cr16/movb.cgs b/sim/testsuite/sim/cr16/movb.cgs new file mode 100644 index 00000000000..e235670d5ef --- /dev/null +++ b/sim/testsuite/sim/cr16/movb.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for movb $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global movb +movb: + movb $1, r4 + movb $0, r5 + + movb r4, r5 + + test_h_gr r5, 1 + + pass diff --git a/sim/testsuite/sim/cr16/movd.cgs b/sim/testsuite/sim/cr16/movd.cgs new file mode 100644 index 00000000000..8e77b5ab5f0 --- /dev/null +++ b/sim/testsuite/sim/cr16/movd.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for movd $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global movd +movd: + movd $0x12345678, (r4,r3) + + movd (r4,r3), (r6,r5) + + test_h_grp "(r6,r5)", 0x12345678 + + pass diff --git a/sim/testsuite/sim/cr16/movw.cgs b/sim/testsuite/sim/cr16/movw.cgs new file mode 100644 index 00000000000..cd92cba6d42 --- /dev/null +++ b/sim/testsuite/sim/cr16/movw.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for movw $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global movw +movw: + movw $0x1234, r4 + + movw r4, r5 + + test_h_gr r5, 0x1234 + + pass diff --git a/sim/testsuite/sim/cr16/movxb.cgs b/sim/testsuite/sim/cr16/movxb.cgs new file mode 100644 index 00000000000..301e9af48fe --- /dev/null +++ b/sim/testsuite/sim/cr16/movxb.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for movb $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global movb +movb: + movb $0xf, r4 + movw $0x1234, r5 + + movxb r4, r5 + + test_h_gr r5, 0xf + + pass diff --git a/sim/testsuite/sim/cr16/movxw.cgs b/sim/testsuite/sim/cr16/movxw.cgs new file mode 100644 index 00000000000..44d95495340 --- /dev/null +++ b/sim/testsuite/sim/cr16/movxw.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for movw $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global movw +movw: + movw $0x1234, r4 + movd $0, (r6,r5) + + movxw r4, (r6,r5) + + test_h_grp "(r6, r5)", 0x1234 + + pass diff --git a/sim/testsuite/sim/cr16/movzb.cgs b/sim/testsuite/sim/cr16/movzb.cgs new file mode 100644 index 00000000000..e4de4b06e66 --- /dev/null +++ b/sim/testsuite/sim/cr16/movzb.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for movb $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global movb +movb: + movw $0x120f, r4 + movw $0x1200, r5 + + movzb r4, r5 + + test_h_gr r5, 0xf + + pass diff --git a/sim/testsuite/sim/cr16/movzw.cgs b/sim/testsuite/sim/cr16/movzw.cgs new file mode 100644 index 00000000000..f3f58351653 --- /dev/null +++ b/sim/testsuite/sim/cr16/movzw.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for movw $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global movw +movw: + movb $0xff, r4 + movd $0x12345678,(r6, r5) + + movzw r4, (r6,r5) + + test_h_grp "(r6, r5)", 0xff + + pass diff --git a/sim/testsuite/sim/cr16/mulb.cgs b/sim/testsuite/sim/cr16/mulb.cgs new file mode 100644 index 00000000000..6b77cb25ffb --- /dev/null +++ b/sim/testsuite/sim/cr16/mulb.cgs @@ -0,0 +1,30 @@ +# cr16 testcase for mulb $imm4/imm16/reg,$reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global mulb +mulb: + movw $0x2303,r4 + movw $0x1207,r5 + + mulb r4, r5 + cmpb $21, r5 + beq ok1 +not_ok: + fail + +ok1: + movw $3,r4 + mulb $7,r4 + cmpb $21, r4 + beq ok + br not_ok +ok: + movw $3,r4 + mulb $0x1207, r4 + test_h_gr r4, 21 + + pass diff --git a/sim/testsuite/sim/cr16/mulsb.cgs b/sim/testsuite/sim/cr16/mulsb.cgs new file mode 100644 index 00000000000..60912af2e25 --- /dev/null +++ b/sim/testsuite/sim/cr16/mulsb.cgs @@ -0,0 +1,24 @@ +# cr16 testcase for mulsb $imm4/imm16/reg, reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global mulsb +mulsb: + movw $-3,r4 + movw $7,r5 + + mulsb r4, r5 + cmpw $-21, r5 + beq ok1 +not_ok: + fail + +ok1: + movw $3,r4 + mulw $7, r4 + test_h_gr r4, 21 + + pass diff --git a/sim/testsuite/sim/cr16/mulsw.cgs b/sim/testsuite/sim/cr16/mulsw.cgs new file mode 100644 index 00000000000..5bf5ac15fa0 --- /dev/null +++ b/sim/testsuite/sim/cr16/mulsw.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for mulsw reg, (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global mulsw +mulsw: + movw $0xfff,r4 # fix for 0xffff + movd $0xffffffff,(r6,r5) + + mulsw r4, (r6,r5) + test_h_grp "(r6,r5)", 0xfffff001 + + pass diff --git a/sim/testsuite/sim/cr16/muluw.cgs b/sim/testsuite/sim/cr16/muluw.cgs new file mode 100644 index 00000000000..3005a98594b --- /dev/null +++ b/sim/testsuite/sim/cr16/muluw.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for mul $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global mul +mul: + movw $0xfff,r4 # fix for 0xffff + movd $0xffffffff,(r6,r5) + + muluw r4, (r6,r5) + test_h_grp "(r6,r5)", 0xfffff001 + + pass diff --git a/sim/testsuite/sim/cr16/mulw.cgs b/sim/testsuite/sim/cr16/mulw.cgs new file mode 100644 index 00000000000..bee87faf80d --- /dev/null +++ b/sim/testsuite/sim/cr16/mulw.cgs @@ -0,0 +1,23 @@ +# cr16 testcase for mul $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global mul +mul: + movw $0x1234,r4 + movw $0x1234,r5 + + mulw r4, r5 + cmpw $0x5a90, r5 + beq ok1 +not_ok: + fail + +ok1: + mulw $0x1234, r4 + test_h_gr r4, 0x5a90 + + pass diff --git a/sim/testsuite/sim/cr16/nop.cgs b/sim/testsuite/sim/cr16/nop.cgs new file mode 100644 index 00000000000..e29fa93f7d0 --- /dev/null +++ b/sim/testsuite/sim/cr16/nop.cgs @@ -0,0 +1,11 @@ +# cr16 testcase for nop +# mach(): cr16 + + .include "testutils.inc" + + start + + .global nop +nop: + nop + pass diff --git a/sim/testsuite/sim/cr16/orb.cgs b/sim/testsuite/sim/cr16/orb.cgs new file mode 100644 index 00000000000..61f7f6e3e89 --- /dev/null +++ b/sim/testsuite/sim/cr16/orb.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for or $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global or +or: + movb $3, r4 + movb $6, r5 + + orb r4,r5 + + test_h_gr r5, 7 + + pass diff --git a/sim/testsuite/sim/cr16/ord.cgs b/sim/testsuite/sim/cr16/ord.cgs new file mode 100644 index 00000000000..b295f045fcc --- /dev/null +++ b/sim/testsuite/sim/cr16/ord.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for or $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global or +or: + movd $0x33333333, (r4,r3) + movd $0x66666666, (r6,r5) + + ord (r4,r3), (r6,r5) + + test_h_grp "(r6,r5)", 0x77777777 + + pass diff --git a/sim/testsuite/sim/cr16/orw.cgs b/sim/testsuite/sim/cr16/orw.cgs new file mode 100644 index 00000000000..138af881bde --- /dev/null +++ b/sim/testsuite/sim/cr16/orw.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for or $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global or +or: + movw $3, r4 + movw $6, r5 + + orw r4, r5 + + test_h_gr r5, 7 + + pass diff --git a/sim/testsuite/sim/cr16/pop1.cgs b/sim/testsuite/sim/cr16/pop1.cgs new file mode 100644 index 00000000000..9ac46300e45 --- /dev/null +++ b/sim/testsuite/sim/cr16/pop1.cgs @@ -0,0 +1,40 @@ +# cr16 testcase for pop count reg RA insns. +# mach: cr16 + + .include "testutils.inc" + + start +pop1: + movd $0x1000, (sp) + movw $0x2f50, r3 + storw r3, 0x1000 + movw $0x107e, r3 + storw r3, 0x1002 + movw $0x35ec, r3 + storw r3, 0x1004 + + movd $0xabcd, (r3,r2) + stord (r3,r2), 0x1006 + + pop $3,r5, RA + + cmpw $0x2f50,r5 + beq ok1 + br not_ok +not_ok: + fail +ok1: + cmpw $0x107e,r6 + beq ok2 + br not_ok +ok2: + cmpw $0x35ec,r7 + beq ok3 + br not_ok + +ok3: + cmpd $0xabcd, (ra) + beq ok4 + br not_ok +ok4: + pass diff --git a/sim/testsuite/sim/cr16/pop2.cgs b/sim/testsuite/sim/cr16/pop2.cgs new file mode 100644 index 00000000000..808f01e9a2e --- /dev/null +++ b/sim/testsuite/sim/cr16/pop2.cgs @@ -0,0 +1,33 @@ +# cr16 testcase for pop count reg insns. +# mach: cr16 + + .include "testutils.inc" + + start +pop2: + movd $0x1000, (sp) + movw $0x2f50, r3 + storw r3, 0x1000 + movw $0x107e, r3 + storw r3, 0x1002 + movw $0x35ec, r3 + storw r3, 0x1004 + + pop $3,r5 + + cmpw $0x2f50,r5 + beq ok1 + br not_ok +not_ok: + fail +ok1: + cmpw $0x107e,r6 + beq ok2 + br not_ok +ok2: + cmpw $0x35ec,r7 + beq ok3 + br not_ok + +ok3: + pass diff --git a/sim/testsuite/sim/cr16/pop3.cgs b/sim/testsuite/sim/cr16/pop3.cgs new file mode 100644 index 00000000000..35d893dae95 --- /dev/null +++ b/sim/testsuite/sim/cr16/pop3.cgs @@ -0,0 +1,22 @@ +# cr16 testcase for pop RA insns. +# mach: cr16 + + .include "testutils.inc" + + start +pop3: + movd $0x1006, (sp) + movd $0xabcd, (r3,r2) + stord (r3,r2), 0x1006 + pop RA + + + cmpd $0xabcd, (ra) + beq ok + br not_ok +not_ok: + fail +ok: + pass + + diff --git a/sim/testsuite/sim/cr16/popret1.cgs b/sim/testsuite/sim/cr16/popret1.cgs new file mode 100644 index 00000000000..aab42b30a23 --- /dev/null +++ b/sim/testsuite/sim/cr16/popret1.cgs @@ -0,0 +1,38 @@ +# cr16 testcase for popret count reg RA insns. +# mach: cr16 + + .include "testutils.inc" + + start +popret1: + movd $0x1000, (sp) + movw $0x2f50, r3 + storw r3, 0x1000 + movw $0x107e, r3 + storw r3, 0x1002 + movw $0x35ec, r3 + storw r3, 0x1004 + + movd $ok, (r3,r2) # jump to ok + lshd $-1, (r3,r2) + stord (r3,r2), 0x1006 + + popret $3,r5, RA + +ok: + cmpw $0x2f50,r5 + beq ok1 + br not_ok +not_ok: + fail +ok1: + cmpw $0x107e,r6 + beq ok2 + br not_ok +ok2: + cmpw $0x35ec,r7 + beq ok3 + br not_ok + +ok3: + pass diff --git a/sim/testsuite/sim/cr16/popret2.cgs b/sim/testsuite/sim/cr16/popret2.cgs new file mode 100644 index 00000000000..5ad65c548ff --- /dev/null +++ b/sim/testsuite/sim/cr16/popret2.cgs @@ -0,0 +1,38 @@ +# cr16 testcase for popret count reg insns. +# mach: cr16 + + .include "testutils.inc" + + start +popret2: + movd $0x1000, (sp) + movw $0x2f50, r3 + storw r3, 0x1000 + movw $0x107e, r3 + storw r3, 0x1002 + movw $0x35ec, r3 + storw r3, 0x1004 + + movd $ok, (ra) + lshd $-1, (ra) + stord (ra), 0x1006 + + popret $3,r5 + +ok: + cmpw $0x2f50,r5 + beq ok1 + br not_ok +not_ok: + fail +ok1: + cmpw $0x107e,r6 + beq ok2 + br not_ok +ok2: + cmpw $0x35ec,r7 + beq ok3 + br not_ok + +ok3: + pass diff --git a/sim/testsuite/sim/cr16/popret3.cgs b/sim/testsuite/sim/cr16/popret3.cgs new file mode 100644 index 00000000000..c9c79df8c01 --- /dev/null +++ b/sim/testsuite/sim/cr16/popret3.cgs @@ -0,0 +1,15 @@ +# cr16 testcase for popret RA insns. +# mach: cr16 + + .include "testutils.inc" + + start +popret3: + movd $0x1006, (sp) + movd $ok, (ra) + lshd $-1, (ra) + stord (ra), 0x1006 + popret RA + +ok: + pass diff --git a/sim/testsuite/sim/cr16/push1.cgs b/sim/testsuite/sim/cr16/push1.cgs new file mode 100644 index 00000000000..025a69f2a84 --- /dev/null +++ b/sim/testsuite/sim/cr16/push1.cgs @@ -0,0 +1,39 @@ +# cr16 testcase for push count reg RA insns. +# mach: cr16 + + .include "testutils.inc" + + start +push1: + movd $0x100a, (sp) + movd $0xabcd, (ra) + movw $0x2f50, r5 + movw $0x107e, r6 + movw $0x35ed, r7 + push $3,r5,RA + + loadw 0x1000, r3 + cmpw r3,r5 + beq ok1 + br not_ok +not_ok: + fail +ok1: + loadw 0x1002, r3 + cmpw r3,r6 + beq ok2 + br not_ok +ok2: + loadw 0x1004, r3 + cmpw r3,r7 + beq ok3 + br not_ok + +ok3: + loadd 0x1006, (r3,r2) + cmpd (r3,r2), (ra) + beq ok4 + br not_ok + +ok4: + pass diff --git a/sim/testsuite/sim/cr16/push2.cgs b/sim/testsuite/sim/cr16/push2.cgs new file mode 100644 index 00000000000..d6bd1b66074 --- /dev/null +++ b/sim/testsuite/sim/cr16/push2.cgs @@ -0,0 +1,34 @@ +# cr16 testcase for push count reg insns. +# mach: cr16 + + .include "testutils.inc" + + start +push2: + movd $0x1006, (sp) + movw $0x2f50, r5 + movw $0x107e, r6 + movw $0x35ed, r7 + push $3,r5 + + loadw 0x1000, r3 + cmpw r3,r5 + beq ok1 + br not_ok +not_ok: + fail +ok1: + loadw 0x1002, r3 + cmpw r3,r6 + beq ok2 + br not_ok +ok2: + loadw 0x1004, r3 + cmpw r3,r7 + beq ok3 + br not_ok + +ok3: + pass + + diff --git a/sim/testsuite/sim/cr16/push3.cgs b/sim/testsuite/sim/cr16/push3.cgs new file mode 100644 index 00000000000..6dbf04d9c35 --- /dev/null +++ b/sim/testsuite/sim/cr16/push3.cgs @@ -0,0 +1,22 @@ +# cr16 testcase for push RA insns. +# mach: cr16 + + .include "testutils.inc" + + start +push1: + movd $0x1006, (sp) + movd $0xabcd, (ra) + push RA + + + loadd 0x1002, (r3,r2) + cmpd (r3,r2), (ra) + beq ok + br not_ok +not_ok: + fail +ok: + pass + + diff --git a/sim/testsuite/sim/cr16/ret.cgs b/sim/testsuite/sim/cr16/ret.cgs new file mode 100644 index 00000000000..9e24aa219d6 --- /dev/null +++ b/sim/testsuite/sim/cr16/ret.cgs @@ -0,0 +1,91 @@ +# cr16 testcase for ret +# mach: cr16 + + .include "testutils.inc" + + start + + .global ret +ret: + set_spr_addr ok1,lr + set_icc 0x0 0 + ret + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + ret + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + ret + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + ret + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + ret + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + ret + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + ret + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + ret + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + ret + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + ret + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + ret + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + ret + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + ret + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + ret + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + ret + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + ret + fail +okg: + + pass diff --git a/sim/testsuite/sim/cr16/scc.cgs b/sim/testsuite/sim/cr16/scc.cgs new file mode 100644 index 00000000000..ac592e0a77f --- /dev/null +++ b/sim/testsuite/sim/cr16/scc.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for scc reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global scc +scc: + mvi_h_condbit 0 + movw $12, r4 + movw $10, r5 + cmpw r4, r5 + scc r3 + + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/scs.cgs b/sim/testsuite/sim/cr16/scs.cgs new file mode 100644 index 00000000000..a34e0943e3c --- /dev/null +++ b/sim/testsuite/sim/cr16/scs.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for scs reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global scs +scs: + mvi_h_condbit 0 + movw $12, r4 + movw $10, r5 + subw r4, r5 + scs r3 + + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/seq.cgs b/sim/testsuite/sim/cr16/seq.cgs new file mode 100644 index 00000000000..1b4ad790bbc --- /dev/null +++ b/sim/testsuite/sim/cr16/seq.cgs @@ -0,0 +1,20 @@ +# cr16 testcase for seq reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global seq +seq: + mvi_h_condbit 0 + movw $12, r4 + movw $12, r5 + cmpw r4, r5 + seq r3 + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/sfc.cgs b/sim/testsuite/sim/cr16/sfc.cgs new file mode 100644 index 00000000000..1221f8e7a47 --- /dev/null +++ b/sim/testsuite/sim/cr16/sfc.cgs @@ -0,0 +1,20 @@ +# cr16 testcase for sfc rep +# mach(): cr16 + + .include "testutils.inc" + + start + + .global sfc +sfc: + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + subw r4, r5 + sfc r3 + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/sfs.cgs b/sim/testsuite/sim/cr16/sfs.cgs new file mode 100644 index 00000000000..5663bfb06b4 --- /dev/null +++ b/sim/testsuite/sim/cr16/sfs.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for sfs reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global sfs +sfs: + mvi_h_condbit 0 + movw $0xaa, r4 + movw $0xaa, r5 + addb r4, r5 + sfs r3 + + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/sge.cgs b/sim/testsuite/sim/cr16/sge.cgs new file mode 100644 index 00000000000..7a6565871cd --- /dev/null +++ b/sim/testsuite/sim/cr16/sge.cgs @@ -0,0 +1,20 @@ +# cr16 testcase for sge reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global sge +sge: + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + sge r3 + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/sgt.cgs b/sim/testsuite/sim/cr16/sgt.cgs new file mode 100644 index 00000000000..cc47ea3a2ba --- /dev/null +++ b/sim/testsuite/sim/cr16/sgt.cgs @@ -0,0 +1,20 @@ +# cr16 testcase for sgt reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global sgt +sgt: + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + sgt r3 + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/shi.cgs b/sim/testsuite/sim/cr16/shi.cgs new file mode 100644 index 00000000000..5188a5195a7 --- /dev/null +++ b/sim/testsuite/sim/cr16/shi.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for shi reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global shi +shi: + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + shi r3 + + cmpw $1,r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/shs.cgs b/sim/testsuite/sim/cr16/shs.cgs new file mode 100644 index 00000000000..2a103244697 --- /dev/null +++ b/sim/testsuite/sim/cr16/shs.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for shs reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global shs +shs: + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + subw r4, r5 + shs r3 + + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/slo.cgs b/sim/testsuite/sim/cr16/slo.cgs new file mode 100644 index 00000000000..4e9332aeb5d --- /dev/null +++ b/sim/testsuite/sim/cr16/slo.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for slo reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global slo +slo: + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + slo r3 + + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/sls.cgs b/sim/testsuite/sim/cr16/sls.cgs new file mode 100644 index 00000000000..aab309c59ae --- /dev/null +++ b/sim/testsuite/sim/cr16/sls.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for sls reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global sls +sls: + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + sls r3 + + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/slt.cgs b/sim/testsuite/sim/cr16/slt.cgs new file mode 100644 index 00000000000..a4fa1b5cf9f --- /dev/null +++ b/sim/testsuite/sim/cr16/slt.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for slt rep +# mach(): cr16 + + .include "testutils.inc" + + start + + .global slt +slt: + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + slt r3 + + cmpw $1,r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/sne.cgs b/sim/testsuite/sim/cr16/sne.cgs new file mode 100644 index 00000000000..0d2ccc5021a --- /dev/null +++ b/sim/testsuite/sim/cr16/sne.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for sne reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global sne +sne: + mvi_h_condbit 0 + movw $0, r4 + movw $1, r5 + cmpw r4, r5 + sne r3 + + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/sim/cr16/storb.cgs b/sim/testsuite/sim/cr16/storb.cgs new file mode 100644 index 00000000000..289055dd7a9 --- /dev/null +++ b/sim/testsuite/sim/cr16/storb.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for st $src1,@$src2 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global st +st: + movd $data_loc, (r4,r3) + movw $1,r5 + + storw r5, 0(r4,r3) + + loadw 0(r4,r3),r1 + test_h_gr r1, 1 + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/sim/cr16/stord.cgs b/sim/testsuite/sim/cr16/stord.cgs new file mode 100644 index 00000000000..64f40c1ce10 --- /dev/null +++ b/sim/testsuite/sim/cr16/stord.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for st $src1,@$src2 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global st +st: + movd $data_loc, (r4,r3) + movd $0x12345678, (r6,r5) + + stord (r6,r5),0(r4,r3) + + loadd 0(r4,r3), (r1,r0) + test_h_grp "( r1,r0)", 0x12345678 + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/sim/cr16/storw.cgs b/sim/testsuite/sim/cr16/storw.cgs new file mode 100644 index 00000000000..92876361ffe --- /dev/null +++ b/sim/testsuite/sim/cr16/storw.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for st $src1,@$src2 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global st +st: + movd $data_loc, (r4,r3) + movw $0x1234,r5 + + storw r5,0(r4,r3) + + loadw 0(r4,r3),r1 + test_h_gr r1, 0x1234 + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/sim/cr16/subb.cgs b/sim/testsuite/sim/cr16/subb.cgs new file mode 100644 index 00000000000..6a893ddedc8 --- /dev/null +++ b/sim/testsuite/sim/cr16/subb.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for subb $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global subb +subb: + + movb $7, r4 + movb $3, r5 + + subb r5, r4 + + test_h_gr r4, 4 + + pass diff --git a/sim/testsuite/sim/cr16/subd.cgs b/sim/testsuite/sim/cr16/subd.cgs new file mode 100644 index 00000000000..2e2a33428df --- /dev/null +++ b/sim/testsuite/sim/cr16/subd.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for subd $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global subd +subd: + + movd $0x12345678, (r4,r3) + movd $0x11111111, (r6,r5) + + subd (r6,r5), (r4,r3) + + test_h_grp "(r4,r3)", 0x1234567 + + pass diff --git a/sim/testsuite/sim/cr16/subi.cgs b/sim/testsuite/sim/cr16/subi.cgs new file mode 100644 index 00000000000..5d0fa1a14e8 --- /dev/null +++ b/sim/testsuite/sim/cr16/subi.cgs @@ -0,0 +1,30 @@ +# cr16 testcase for addi #$simm8, $dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global addi +addi: + + movb $1, r4 + addb $2, r4 + + cmpb $3,r4 + bne not_ok + + movw $0x1234, r5 + addw $0x1234, r5 + test_h_gr r5, 0x2468 + + pass + + movd $0x12345678, (r5,r4) + addd $0x12345678, (r5,r4) + test_h_grp "(r5,r4)", 0x2468acf0 + + pass + +not_ok: + fail diff --git a/sim/testsuite/sim/cr16/subw.cgs b/sim/testsuite/sim/cr16/subw.cgs new file mode 100644 index 00000000000..12a12293b3c --- /dev/null +++ b/sim/testsuite/sim/cr16/subw.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for subw $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global subw +subw: + + movw $0x1234, r4 + movw $0x1111, r5 + + subw r5, r4 + + test_h_gr r4, 0x123 + + pass diff --git a/sim/testsuite/sim/cr16/xorb.cgs b/sim/testsuite/sim/cr16/xorb.cgs new file mode 100644 index 00000000000..4ee4b2d5e01 --- /dev/null +++ b/sim/testsuite/sim/cr16/xorb.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for xor $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global xor +xor: + movb $3, r4 + movb $6, r5 + + xorb r4,r5 + + test_h_gr r5, 5 + + pass diff --git a/sim/testsuite/sim/cr16/xord.cgs b/sim/testsuite/sim/cr16/xord.cgs new file mode 100644 index 00000000000..3bbcac0f52b --- /dev/null +++ b/sim/testsuite/sim/cr16/xord.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for xor $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global xor +xor: + movd $0x33333333, (r4,r3) + movd $0x66666666, (r6,r5) + + xord (r4,r3), (r6,r5) + + test_h_grp "(r6,r5)", 0x55555555 + + pass diff --git a/sim/testsuite/sim/cr16/xorw.cgs b/sim/testsuite/sim/cr16/xorw.cgs new file mode 100644 index 00000000000..d82faa3f333 --- /dev/null +++ b/sim/testsuite/sim/cr16/xorw.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for xor $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global xor +xor: + movw $3, r4 + movw $6, r5 + + xorw r4, r5 + + test_h_gr r5, 5 + + pass |