Add fr450 support.

14 files changed, 549 insertions, 1 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index ba6c6ec3638..88886be6a18 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-frv.c (fr400_audio): New variable.
+	(md_parse_option, md_show_usage): Add -mcpu=fr405 and -mcpu=fr450.
+	(md_parse_option): Set fr400_audio for -mcpu=fr400 and -mcpu=fr405.
+	(target_implements_insn_p): New function.
+	(md_assemble): Report an error if the processor doesn't implement
+	the instruction.
+
 2004-02-27  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 
 	* config/tc-m32r.c (md_longopts): Added -no-bitinst option.
diff --git a/gas/config/tc-frv.c b/gas/config/tc-frv.c
index 96e630bf298..6c6528bfb8e 100644
--- a/gas/config/tc-frv.c
+++ b/gas/config/tc-frv.c
@@ -163,6 +163,7 @@ static FRV_VLIW vliw;
 #endif
 
 static unsigned long frv_mach = bfd_mach_frv;
+static bfd_boolean fr400_audio;
 
 /* Flags to set in the elf header */
 static flagword frv_flags = DEFAULT_FLAGS;
@@ -354,10 +355,24 @@ md_parse_option (c, arg)
 	    frv_mach = bfd_mach_fr550;
 	  }
 
+	else if (strcmp (p, "fr450") == 0)
+	  {
+	    cpu_flags = EF_FRV_CPU_FR450;
+	    frv_mach = bfd_mach_fr450;
+	  }
+
+	else if (strcmp (p, "fr405") == 0)
+	  {
+	    cpu_flags = EF_FRV_CPU_FR405;
+	    frv_mach = bfd_mach_fr400;
+	    fr400_audio = TRUE;
+	  }
+
 	else if (strcmp (p, "fr400") == 0)
 	  {
 	    cpu_flags = EF_FRV_CPU_FR400;
 	    frv_mach = bfd_mach_fr400;
+	    fr400_audio = FALSE;
 	  }
 
 	else if (strcmp (p, "fr300") == 0)
@@ -446,7 +461,7 @@ md_show_usage (stream)
   fprintf (stream, _("-mpic        Note small position independent code\n"));
   fprintf (stream, _("-mPIC        Note large position independent code\n"));
   fprintf (stream, _("-mlibrary-pic Compile library for large position indepedent code\n"));
-  fprintf (stream, _("-mcpu={fr500|fr550|fr400|fr300|frv|simple|tomcat}\n"));
+  fprintf (stream, _("-mcpu={fr500|fr550|fr400|fr405|fr450|fr300|frv|simple|tomcat}\n"));
   fprintf (stream, _("             Record the cpu type\n"));
   fprintf (stream, _("-mtomcat-stats Print out stats for tomcat workarounds\n"));
   fprintf (stream, _("-mtomcat-debug Debug tomcat workarounds\n"));
@@ -1042,6 +1057,36 @@ fr550_check_acc_range (FRV_VLIW *vliw, frv_insn *insn)
   return 0; /* all is ok */
 }
 
+/* Return true if the target implements instruction INSN.  */
+
+static bfd_boolean
+target_implements_insn_p (const CGEN_INSN *insn)
+{
+  switch (frv_mach)
+    {
+    default:
+      /* bfd_mach_frv or generic.  */
+      return TRUE;
+
+    case bfd_mach_fr300:
+    case bfd_mach_frvsimple:
+      return CGEN_INSN_MACH_HAS_P (insn, MACH_SIMPLE);
+
+    case bfd_mach_fr400:
+      return ((fr400_audio || !CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_AUDIO))
+	      && CGEN_INSN_MACH_HAS_P (insn, MACH_FR400));
+
+    case bfd_mach_fr450:
+      return CGEN_INSN_MACH_HAS_P (insn, MACH_FR450);
+
+    case bfd_mach_fr500:
+      return CGEN_INSN_MACH_HAS_P (insn, MACH_FR500);
+
+    case bfd_mach_fr550:
+      return CGEN_INSN_MACH_HAS_P (insn, MACH_FR550);
+    }
+}
+
 void
 md_assemble (str)
      char * str;
@@ -1125,6 +1170,11 @@ md_assemble (str)
      instructions, don't do vliw checking.  */
   else if (frv_mach != bfd_mach_frv)
     {
+      if (!target_implements_insn_p (insn.insn))
+	{
+	  as_bad (_("Instruction not supported by this architecture"));
+	  return;
+	}
       packing_constraint = frv_vliw_add_insn (& vliw, insn.insn);
       if (frv_mach == bfd_mach_fr550 && ! packing_constraint)
 	packing_constraint = fr550_check_acc_range (& vliw, & insn);
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 77934e15fdf..a42e38d3e87 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,5 +1,16 @@
 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 
+	* gas/frv/fr405-insn.[sdl]: New test.
+	* gas/frv/fr450-spr.[sd]: New test.
+	* gas/frv/fr450-insn.[sdl]: New test.
+	* gas/frv/fr450-media-issue.[sl]: New test.
+	* gas/frv/allinsn.exp: Run new tests.  Ensure fr405 instructions
+	aren't accepted for -mcpu=fr400 or -mcpu=fr500.  Ensure fr450
+	instructions aren't accepted for -mcpu=fr400, -mcpu=fr405 or
+	-mcpu=fr500.
+
+2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
+
 	* gas/frv/allinsn.s (rstb, rsth, rst, rstd, rstq): Replace with nops.
 	(rstbf, rsthf, rstf, rstdf, rstqf): Likewise.
 	* gas/frv/allinsn.d: Update accordingly.
diff --git a/gas/testsuite/gas/frv/allinsn.exp b/gas/testsuite/gas/frv/allinsn.exp
index a9fc9654416..8684e4c68fa 100644
--- a/gas/testsuite/gas/frv/allinsn.exp
+++ b/gas/testsuite/gas/frv/allinsn.exp
@@ -1,8 +1,30 @@
 # FRV assembler testsuite.
 
+proc run_list_test { name opts } {
+    global srcdir subdir
+    set testname "$name error test ($opts)"
+    gas_run $name.s $opts >&dump.out
+    if {[regexp_diff dump.out $srcdir/$subdir/$name.l]} {
+	fail $testname
+	verbose "output is [file_contents dump.out]" 2
+	return
+    }
+    pass $testname
+}
+
 if [istarget frv*-*-*] {
     run_dump_test "allinsn"
 
     run_dump_test "fdpic"
     run_dump_test "reloc1"
+    run_dump_test "fr405-insn"
+    run_list_test "fr405-insn" "-mcpu=fr400"
+    run_list_test "fr405-insn" "-mcpu=fr500"
+
+    run_dump_test "fr450-spr"
+    run_dump_test "fr450-insn"
+    run_list_test "fr450-insn" "-mcpu=fr405"
+    run_list_test "fr450-insn" "-mcpu=fr400"
+    run_list_test "fr450-insn" "-mcpu=fr500"
+    run_list_test "fr450-media-issue" "-mcpu=fr450"
 }
diff --git a/gas/testsuite/gas/frv/fr405-insn.d b/gas/testsuite/gas/frv/fr405-insn.d
new file mode 100644
index 00000000000..6cc848b3a5d
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr405-insn.d
@@ -0,0 +1,15 @@
+#as: -mcpu=fr405
+#objdump: -dr
+
+.*:     file format elf32-frv
+
+Disassembly of section \.text:
+
+00000000 <.*>:
+.*:	81 18 41 45 	smu gr4,gr5
+.*:	81 18 41 85 	smass gr4,gr5
+.*:	81 18 41 c5 	smsss gr4,gr5
+.*:	8d 18 40 85 	slass gr4,gr5,gr6
+.*:	8b 18 01 04 	scutss gr4,gr5
+.*:	8d 18 40 05 	addss gr4,gr5,gr6
+.*:	8d 18 40 45 	subss gr4,gr5,gr6
diff --git a/gas/testsuite/gas/frv/fr405-insn.l b/gas/testsuite/gas/frv/fr405-insn.l
new file mode 100644
index 00000000000..8c84f80ece9
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr405-insn.l
@@ -0,0 +1,8 @@
+.*: Assembler messages:
+.*:1: Error: Instruction not supported by this architecture
+.*:2: Error: Instruction not supported by this architecture
+.*:3: Error: Instruction not supported by this architecture
+.*:4: Error: Instruction not supported by this architecture
+.*:5: Error: Instruction not supported by this architecture
+.*:6: Error: Instruction not supported by this architecture
+.*:7: Error: Instruction not supported by this architecture
diff --git a/gas/testsuite/gas/frv/fr405-insn.s b/gas/testsuite/gas/frv/fr405-insn.s
new file mode 100644
index 00000000000..acd5ea26c05
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr405-insn.s
@@ -0,0 +1,7 @@
+	smu	gr4,gr5
+	smass	gr4,gr5
+	smsss	gr4,gr5
+	slass	gr4,gr5,gr6
+	scutss	gr4,gr5
+	addss	gr4,gr5,gr6
+	subss	gr4,gr5,gr6
diff --git a/gas/testsuite/gas/frv/fr450-insn.d b/gas/testsuite/gas/frv/fr450-insn.d
new file mode 100644
index 00000000000..5739c892718
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr450-insn.d
@@ -0,0 +1,41 @@
+#as: -mcpu=fr450
+#objdump: -dr
+
+.*:     file format elf32-frv
+
+Disassembly of section \.text:
+
+00000000 <.*>:
+#
+.*:	80 0d f8 00 	lrai gr31,gr0,0x0,0x0,0x0
+.*:	be 0c 08 00 	lrai gr0,gr31,0x0,0x0,0x0
+.*:	80 0c 08 20 	lrai gr0,gr0,0x1,0x0,0x0
+.*:	80 0c 08 10 	lrai gr0,gr0,0x0,0x1,0x0
+.*:	80 0c 08 08 	lrai gr0,gr0,0x0,0x0,0x1
+#
+.*:	80 0d f8 40 	lrad gr31,gr0,0x0,0x0,0x0
+.*:	be 0c 08 40 	lrad gr0,gr31,0x0,0x0,0x0
+.*:	80 0c 08 60 	lrad gr0,gr0,0x1,0x0,0x0
+.*:	80 0c 08 50 	lrad gr0,gr0,0x0,0x1,0x0
+.*:	80 0c 08 48 	lrad gr0,gr0,0x0,0x0,0x1
+#
+.*:	80 0d f9 00 	tlbpr gr31,gr0,0x0,0x0
+.*:	80 0c 09 1f 	tlbpr gr0,gr31,0x0,0x0
+.*:	9c 0c 09 00 	tlbpr gr0,gr0,0x7,0x0
+.*:	82 0c 09 00 	tlbpr gr0,gr0,0x0,0x1
+#
+.*:	81 e1 e4 00 	mqlclrhs fr30,fr0,fr0
+.*:	81 e0 04 1e 	mqlclrhs fr0,fr30,fr0
+.*:	bd e0 04 00 	mqlclrhs fr0,fr0,fr30
+#
+.*:	81 e1 e5 00 	mqlmths fr30,fr0,fr0
+.*:	81 e0 05 1e 	mqlmths fr0,fr30,fr0
+.*:	bd e0 05 00 	mqlmths fr0,fr0,fr30
+#
+.*:	81 e1 e4 40 	mqsllhi fr30,0x0,fr0
+.*:	81 e0 04 7f 	mqsllhi fr0,0x3f,fr0
+.*:	bd e0 04 40 	mqsllhi fr0,0x0,fr30
+#
+.*:	81 e1 e4 c0 	mqsrahi fr30,0x0,fr0
+.*:	81 e0 04 ff 	mqsrahi fr0,0x3f,fr0
+.*:	bd e0 04 c0 	mqsrahi fr0,0x0,fr30
diff --git a/gas/testsuite/gas/frv/fr450-insn.l b/gas/testsuite/gas/frv/fr450-insn.l
new file mode 100644
index 00000000000..106a8f7041e
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr450-insn.l
@@ -0,0 +1,33 @@
+.*: Assembler messages:
+.*:1: Error: Instruction not supported by this architecture
+.*:2: Error: Instruction not supported by this architecture
+.*:3: Error: Instruction not supported by this architecture
+.*:4: Error: Instruction not supported by this architecture
+.*:5: Error: Instruction not supported by this architecture
+#
+.*:7: Error: Instruction not supported by this architecture
+.*:8: Error: Instruction not supported by this architecture
+.*:9: Error: Instruction not supported by this architecture
+.*:10: Error: Instruction not supported by this architecture
+.*:11: Error: Instruction not supported by this architecture
+#
+.*:13: Error: Instruction not supported by this architecture
+.*:14: Error: Instruction not supported by this architecture
+.*:15: Error: Instruction not supported by this architecture
+.*:16: Error: Instruction not supported by this architecture
+#
+.*:18: Error: Instruction not supported by this architecture
+.*:19: Error: Instruction not supported by this architecture
+.*:20: Error: Instruction not supported by this architecture
+#
+.*:22: Error: Instruction not supported by this architecture
+.*:23: Error: Instruction not supported by this architecture
+.*:24: Error: Instruction not supported by this architecture
+#
+.*:26: Error: Instruction not supported by this architecture
+.*:27: Error: Instruction not supported by this architecture
+.*:28: Error: Instruction not supported by this architecture
+#
+.*:30: Error: Instruction not supported by this architecture
+.*:31: Error: Instruction not supported by this architecture
+.*:32: Error: Instruction not supported by this architecture
diff --git a/gas/testsuite/gas/frv/fr450-insn.s b/gas/testsuite/gas/frv/fr450-insn.s
new file mode 100644
index 00000000000..7224c30ca80
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr450-insn.s
@@ -0,0 +1,32 @@
+	lrai	gr31,gr0,#0,#0,#0
+	lrai	gr0,gr31,#0,#0,#0
+	lrai	gr0,gr0,#1,#0,#0
+	lrai	gr0,gr0,#0,#1,#0
+	lrai	gr0,gr0,#0,#0,#1
+
+	lrad	gr31,gr0,#0,#0,#0
+	lrad	gr0,gr31,#0,#0,#0
+	lrad	gr0,gr0,#1,#0,#0
+	lrad	gr0,gr0,#0,#1,#0
+	lrad	gr0,gr0,#0,#0,#1
+
+	tlbpr	gr31,gr0,#0,#0
+	tlbpr	gr0,gr31,#0,#0
+	tlbpr	gr0,gr0,#7,#0
+	tlbpr	gr0,gr0,#0,#1
+
+	mqlclrhs fr30,fr0,fr0
+	mqlclrhs fr0,fr30,fr0
+	mqlclrhs fr0,fr0,fr30
+
+	mqlmths	fr30,fr0,fr0
+	mqlmths	fr0,fr30,fr0
+	mqlmths	fr0,fr0,fr30
+
+	mqsllhi	fr30,#0,fr0
+	mqsllhi	fr0,#63,fr0
+	mqsllhi	fr0,#0,fr30
+
+	mqsrahi	fr30,#0,fr0
+	mqsrahi	fr0,#63,fr0
+	mqsrahi	fr0,#0,fr30
diff --git a/gas/testsuite/gas/frv/fr450-media-issue.l b/gas/testsuite/gas/frv/fr450-media-issue.l
new file mode 100644
index 00000000000..679702191bc
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr450-media-issue.l
@@ -0,0 +1,31 @@
+.*: Assembler messages:
+.*:5: Error: VLIW packing constraint violation
+.*:9: Error: VLIW packing constraint violation
+.*:13: Error: VLIW packing constraint violation
+#
+.*:17: Error: VLIW packing constraint violation
+.*:19: Error: VLIW packing constraint violation
+.*:21: Error: VLIW packing constraint violation
+.*:23: Error: VLIW packing constraint violation
+.*:25: Error: VLIW packing constraint violation
+.*:27: Error: VLIW packing constraint violation
+#
+.*:33: Error: VLIW packing constraint violation
+.*:37: Error: VLIW packing constraint violation
+.*:41: Error: VLIW packing constraint violation
+#
+.*:45: Error: VLIW packing constraint violation
+.*:47: Error: VLIW packing constraint violation
+.*:49: Error: VLIW packing constraint violation
+.*:51: Error: VLIW packing constraint violation
+#
+.*:61: Error: VLIW packing constraint violation
+.*:65: Error: VLIW packing constraint violation
+.*:69: Error: VLIW packing constraint violation
+#
+.*:73: Error: VLIW packing constraint violation
+.*:75: Error: VLIW packing constraint violation
+.*:77: Error: VLIW packing constraint violation
+.*:79: Error: VLIW packing constraint violation
+.*:81: Error: VLIW packing constraint violation
+.*:83: Error: VLIW packing constraint violation
diff --git a/gas/testsuite/gas/frv/fr450-media-issue.s b/gas/testsuite/gas/frv/fr450-media-issue.s
new file mode 100644
index 00000000000..e73fc98aa55
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr450-media-issue.s
@@ -0,0 +1,83 @@
+	; M-1 first
+	mand.p     fr0,fr1,fr2	; M1
+	mpackh     fr4,fr5,fr6  ; M1 -- ok
+	mand.p     fr0,fr1,fr2	; M1
+	mcpli      fr4,#1,fr6	; M2 -- error
+	mand.p     fr0,fr1,fr2	; M1
+	mmulhu     fr4,fr6,acc8 ; M3 -- ok
+	mand.p     fr0,fr1,fr2	; M1
+	mqmulhu    fr4,fr6,acc8 ; M4 -- error
+	mand.p     fr0,fr1,fr2	; M1
+	mcuti      acc8,#2,fr8	; M5 -- ok
+	mand.p     fr0,fr1,fr2	; M1
+	mdcutssi   acc8,#2,fr8	; M6 -- error
+
+	; M-2 first
+	mqaddhss.p fr0,fr2,fr2	; M2
+	mpackh     fr4,fr5,fr6  ; M1 -- error
+	mqaddhss.p fr0,fr2,fr2	; M2
+	mcpli      fr4,#1,fr6	; M2 -- error
+	mqaddhss.p fr0,fr2,fr2	; M2
+	mmulhu     fr4,fr6,acc8 ; M3 -- error
+	mqaddhss.p fr0,fr2,fr2	; M2
+	mqmulhu    fr4,fr6,acc8 ; M4 -- error
+	mqaddhss.p fr0,fr2,fr2	; M2
+	mcuti      acc8,#2,fr8	; M5 -- error
+	mqaddhss.p fr0,fr2,fr2	; M2
+	mdcutssi   acc8,#2,fr8	; M6 -- error
+
+	; M-3 first
+	mwtacc.p   fr0,acc0	; M3
+	mpackh     fr4,fr5,fr6  ; M1 -- ok
+	mwtacc.p   fr0,acc0	; M3
+	mcpli      fr4,#1,fr6	; M2 -- error
+	mwtacc.p   fr0,acc0	; M3
+	mmulhu     fr4,fr6,acc8 ; M3 -- ok
+	mwtacc.p   fr0,acc0	; M3
+	mqmulhu    fr4,fr6,acc8 ; M4 -- error
+	mwtacc.p   fr0,acc0	; M3
+	mcuti      acc8,#2,fr8	; M5 -- ok
+	mwtacc.p   fr0,acc0	; M3
+	mdcutssi   acc8,#2,fr8	; M6 -- error
+
+	; M-4 first
+	mqcpxrs.p  fr0,fr2,acc0	; M4
+	mpackh     fr4,fr5,fr6  ; M1 -- error
+	mqcpxrs.p  fr0,fr2,acc0	; M4
+	mcpli      fr4,#1,fr6	; M2 -- error
+	mqcpxrs.p  fr0,fr2,acc0	; M4
+	mmulhu     fr4,fr6,acc8 ; M3 -- error
+	mqcpxrs.p  fr0,fr2,acc0	; M4
+	mqmulhu    fr4,fr6,acc8 ; M4 -- error
+	mqcpxrs.p  fr0,fr2,acc0	; M4
+	mcuti      acc8,#2,fr8	; M5 -- ok
+	mqcpxrs.p  fr0,fr2,acc0	; M4
+	mdcutssi   acc8,#2,fr8	; M6 -- ok
+
+	; M-5 first
+	mrdacc.p   acc0,fr0	; M5
+	mpackh     fr4,fr5,fr6  ; M1 -- ok
+	mrdacc.p   acc0,fr0	; M5
+	mcpli      fr4,#1,fr6	; M2 -- error
+	mrdacc.p   acc0,fr0	; M5
+	mmulhu     fr4,fr6,acc8 ; M3 -- ok
+	mrdacc.p   acc0,fr0	; M5
+	mqmulhu    fr4,fr6,acc8 ; M4 -- error
+	mrdacc.p   acc0,fr0	; M5
+	mcuti      acc8,#2,fr8	; M5 -- ok
+	mrdacc.p   acc0,fr0	; M5
+	mdcutssi   acc8,#2,fr8	; M6 -- error
+
+	; M-6 first
+	mdcutssi.p acc0,#3,fr0	; M6
+	mpackh     fr4,fr5,fr6  ; M1 -- error
+	mdcutssi.p acc0,#3,fr0	; M6
+	mcpli      fr4,#1,fr6	; M2 -- error
+	mdcutssi.p acc0,#3,fr0	; M6
+	mmulhu     fr4,fr6,acc8 ; M3 -- error
+	mdcutssi.p acc0,#3,fr0	; M6
+	mqmulhu    fr4,fr6,acc8 ; M4 -- error
+	mdcutssi.p acc0,#3,fr0	; M6
+	mcuti      acc8,#2,fr8	; M5 -- error
+	mdcutssi.p acc0,#3,fr0	; M6
+	mdcutssi   acc8,#2,fr8	; M6 -- error
diff --git a/gas/testsuite/gas/frv/fr450-spr.d b/gas/testsuite/gas/frv/fr450-spr.d
new file mode 100644
index 00000000000..85b1f092c94
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr450-spr.d
@@ -0,0 +1,107 @@
+#as: -mcpu=fr450
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+.* <\.text>:
+.*:	80 0c 01 84 	movgs gr4,psr
+.*:	80 0c 11 84 	movgs gr4,pcsr
+.*:	80 0c 21 84 	movgs gr4,bpcsr
+.*:	80 0c 31 84 	movgs gr4,tbr
+.*:	80 0c 41 84 	movgs gr4,bpsr
+.*:	80 0d 01 84 	movgs gr4,hsr0
+.*:	88 0c 01 84 	movgs gr4,ccr
+.*:	88 0c 71 84 	movgs gr4,cccr
+.*:	88 0d 01 84 	movgs gr4,lr
+.*:	88 0d 11 84 	movgs gr4,lcr
+.*:	88 0d 81 84 	movgs gr4,iacc0h
+.*:	88 0d 91 84 	movgs gr4,iacc0l
+.*:	88 0e 01 84 	movgs gr4,isr
+.*:	90 0c 01 84 	movgs gr4,epcr0
+.*:	92 0c 01 84 	movgs gr4,esr0
+.*:	92 0c e1 84 	movgs gr4,esr14
+.*:	92 0c f1 84 	movgs gr4,esr15
+.*:	94 0e 11 84 	movgs gr4,esfr1
+.*:	9a 0c 01 84 	movgs gr4,scr0
+.*:	9a 0c 11 84 	movgs gr4,scr1
+.*:	9a 0c 21 84 	movgs gr4,scr2
+.*:	9a 0c 31 84 	movgs gr4,scr3
+.*:	a8 0c 01 84 	movgs gr4,msr0
+.*:	a8 0c 11 84 	movgs gr4,msr1
+.*:	b0 0c 01 84 	movgs gr4,ear0
+.*:	b0 0c f1 84 	movgs gr4,ear15
+.*:	b4 0c 01 84 	movgs gr4,iamlr0
+.*:	b4 0c 11 84 	movgs gr4,iamlr1
+.*:	b4 0c 21 84 	movgs gr4,iamlr2
+.*:	b4 0c 31 84 	movgs gr4,iamlr3
+.*:	b4 0c 41 84 	movgs gr4,iamlr4
+.*:	b4 0c 51 84 	movgs gr4,iamlr5
+.*:	b4 0c 61 84 	movgs gr4,iamlr6
+.*:	b4 0c 71 84 	movgs gr4,iamlr7
+.*:	b6 0c 01 84 	movgs gr4,iampr0
+.*:	b6 0c 11 84 	movgs gr4,iampr1
+.*:	b6 0c 21 84 	movgs gr4,iampr2
+.*:	b6 0c 31 84 	movgs gr4,iampr3
+.*:	b6 0c 41 84 	movgs gr4,iampr4
+.*:	b6 0c 51 84 	movgs gr4,iampr5
+.*:	b6 0c 61 84 	movgs gr4,iampr6
+.*:	b6 0c 71 84 	movgs gr4,iampr7
+.*:	b8 0c 01 84 	movgs gr4,damlr0
+.*:	b8 0c 11 84 	movgs gr4,damlr1
+.*:	b8 0c 21 84 	movgs gr4,damlr2
+.*:	b8 0c 31 84 	movgs gr4,damlr3
+.*:	b8 0c 41 84 	movgs gr4,damlr4
+.*:	b8 0c 51 84 	movgs gr4,damlr5
+.*:	b8 0c 61 84 	movgs gr4,damlr6
+.*:	b8 0c 71 84 	movgs gr4,damlr7
+.*:	b8 0c 81 84 	movgs gr4,damlr8
+.*:	b8 0c 91 84 	movgs gr4,damlr9
+.*:	b8 0c a1 84 	movgs gr4,damlr10
+.*:	b8 0c b1 84 	movgs gr4,damlr11
+.*:	ba 0c 01 84 	movgs gr4,dampr0
+.*:	ba 0c 11 84 	movgs gr4,dampr1
+.*:	ba 0c 21 84 	movgs gr4,dampr2
+.*:	ba 0c 31 84 	movgs gr4,dampr3
+.*:	ba 0c 41 84 	movgs gr4,dampr4
+.*:	ba 0c 51 84 	movgs gr4,dampr5
+.*:	ba 0c 61 84 	movgs gr4,dampr6
+.*:	ba 0c 71 84 	movgs gr4,dampr7
+.*:	ba 0c 81 84 	movgs gr4,dampr8
+.*:	ba 0c 91 84 	movgs gr4,dampr9
+.*:	ba 0c a1 84 	movgs gr4,dampr10
+.*:	ba 0c b1 84 	movgs gr4,dampr11
+.*:	bc 0c 01 84 	movgs gr4,amcr
+.*:	bc 0c 51 84 	movgs gr4,iamvr1
+.*:	bc 0c 71 84 	movgs gr4,damvr1
+.*:	bc 0d 01 84 	movgs gr4,cxnr
+.*:	bc 0d 11 84 	movgs gr4,ttbr
+.*:	bc 0d 21 84 	movgs gr4,tplr
+.*:	bc 0d 31 84 	movgs gr4,tppr
+.*:	bc 0d 41 84 	movgs gr4,tpxr
+.*:	bc 0e 01 84 	movgs gr4,timerh
+.*:	bc 0e 11 84 	movgs gr4,timerl
+.*:	bc 0e 21 84 	movgs gr4,timerd
+.*:	c0 0c 01 84 	movgs gr4,dcr
+.*:	c0 0c 11 84 	movgs gr4,brr
+.*:	c0 0c 21 84 	movgs gr4,nmar
+.*:	c0 0c 31 84 	movgs gr4,btbr
+.*:	c0 0c 41 84 	movgs gr4,ibar0
+.*:	c0 0c 51 84 	movgs gr4,ibar1
+.*:	c0 0c 61 84 	movgs gr4,ibar2
+.*:	c0 0c 71 84 	movgs gr4,ibar3
+.*:	c0 0c 81 84 	movgs gr4,dbar0
+.*:	c0 0c 91 84 	movgs gr4,dbar1
+.*:	c0 0c a1 84 	movgs gr4,dbar2
+.*:	c0 0c b1 84 	movgs gr4,dbar3
+.*:	c0 0c c1 84 	movgs gr4,dbdr00
+.*:	c0 0c d1 84 	movgs gr4,dbdr01
+.*:	c0 0c e1 84 	movgs gr4,dbdr02
+.*:	c0 0c f1 84 	movgs gr4,dbdr03
+.*:	c0 0d 01 84 	movgs gr4,dbdr10
+.*:	c0 0d 11 84 	movgs gr4,dbdr11
+.*:	c0 0d c1 84 	movgs gr4,dbmr00
+.*:	c0 0d d1 84 	movgs gr4,dbmr01
+.*:	c0 0e 01 84 	movgs gr4,dbmr10
+.*:	c0 0e 11 84 	movgs gr4,dbmr11
diff --git a/gas/testsuite/gas/frv/fr450-spr.s b/gas/testsuite/gas/frv/fr450-spr.s
new file mode 100644
index 00000000000..2be3ba65070
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr450-spr.s
@@ -0,0 +1,99 @@
+	movgs	gr4, psr	; 0x000 00000
+	movgs	gr4, pcsr	; 0x001 00001
+	movgs	gr4, bpcsr	; 0x002 00002
+	movgs	gr4, tbr	; 0x003 00003
+	movgs	gr4, bpsr	; 0x004 00004
+	movgs	gr4, hsr0	; 0x010 00020
+	movgs	gr4, ccr	; 0x100 00400
+	movgs	gr4, cccr	; 0x107 00407
+	movgs	gr4, lr		; 0x110 00420
+	movgs	gr4, lcr	; 0x111 00421
+	movgs	gr4, iacc0h	; 0x118 00430
+	movgs	gr4, iacc0l	; 0x119 00431
+	movgs	gr4, isr	; 0x120 00440
+	movgs	gr4, epcr0	; 0x200 01000
+	movgs	gr4, esr0	; 0x240 01100
+	movgs	gr4, esr14	; 0x24e 01116
+	movgs	gr4, esr15	; 0x24f 01117
+	movgs	gr4, esfr1	; 0x2a1 01241
+	movgs	gr4, scr0	; 0x340 01500
+	movgs	gr4, scr1	; 0x341 01501
+	movgs	gr4, scr2	; 0x342 01502
+	movgs	gr4, scr3	; 0x343 01503
+	movgs	gr4, msr0	; 0x500 02400
+	movgs	gr4, msr1	; 0x501 02401
+	movgs	gr4, ear0	; 0x600 03000
+	movgs	gr4, ear15	; 0x60f 03017
+	movgs	gr4, iamlr0	; 0x680 03200
+	movgs	gr4, iamlr1	; 0x681 03201
+	movgs	gr4, iamlr2	; 0x682 03202
+	movgs	gr4, iamlr3	; 0x683 03203
+	movgs	gr4, iamlr4	; 0x684 03204
+	movgs	gr4, iamlr5	; 0x685 03205
+	movgs	gr4, iamlr6	; 0x686 03206
+	movgs	gr4, iamlr7	; 0x687 03207
+	movgs	gr4, iampr0	; 0x6c0 03300
+	movgs	gr4, iampr1	; 0x6c1 03301
+	movgs	gr4, iampr2	; 0x6c2 03302
+	movgs	gr4, iampr3	; 0x6c3 03303
+	movgs	gr4, iampr4	; 0x6c4 03304
+	movgs	gr4, iampr5	; 0x6c5 03305
+	movgs	gr4, iampr6	; 0x6c6 03306
+	movgs	gr4, iampr7	; 0x6c7 03307
+	movgs	gr4, damlr0	; 0x700 03400
+	movgs	gr4, damlr1	; 0x701 03401
+	movgs	gr4, damlr2	; 0x702 03402
+	movgs	gr4, damlr3	; 0x703 03403
+	movgs	gr4, damlr4	; 0x704 03404
+	movgs	gr4, damlr5	; 0x705 03405
+	movgs	gr4, damlr6	; 0x706 03406
+	movgs	gr4, damlr7	; 0x707 03407
+	movgs	gr4, damlr8	; 0x708 03410
+	movgs	gr4, damlr9	; 0x709 03411
+	movgs	gr4, damlr10	; 0x70a 03412
+	movgs	gr4, damlr11	; 0x70b 03413
+	movgs	gr4, dampr0	; 0x740 03500
+	movgs	gr4, dampr1	; 0x741 03501
+	movgs	gr4, dampr2	; 0x742 03502
+	movgs	gr4, dampr3	; 0x743 03503
+	movgs	gr4, dampr4	; 0x744 03504
+	movgs	gr4, dampr5	; 0x745 03505
+	movgs	gr4, dampr6	; 0x746 03506
+	movgs	gr4, dampr7	; 0x747 03507
+	movgs	gr4, dampr8	; 0x748 03510
+	movgs	gr4, dampr9	; 0x749 03511
+	movgs	gr4, dampr10	; 0x74a 03512
+	movgs	gr4, dampr11	; 0x74b 03513
+	movgs	gr4, amcr	; 0x780 03600
+	movgs	gr4, iamvr1	; 0x785 03605
+	movgs	gr4, damvr1	; 0x787 03607
+	movgs	gr4, cxnr	; 0x790 03620
+	movgs	gr4, ttbr	; 0x791 03621
+	movgs	gr4, tplr	; 0x792 03622
+	movgs	gr4, tppr	; 0x793 03623
+	movgs	gr4, tpxr	; 0x794 03624
+	movgs	gr4, timerh	; 0x7a0 03640
+	movgs	gr4, timerl	; 0x7a1 03641
+	movgs	gr4, timerd	; 0x7a2 03642
+	movgs	gr4, dcr	; 0x800 04000
+	movgs	gr4, brr	; 0x801 04001
+	movgs	gr4, nmar	; 0x802 04002
+	movgs	gr4, btbr	; 0x803 04003
+	movgs	gr4, ibar0	; 0x804 04004
+	movgs	gr4, ibar1	; 0x805 04005
+	movgs	gr4, ibar2	; 0x806 04006
+	movgs	gr4, ibar3	; 0x807 04007
+	movgs	gr4, dbar0	; 0x808 04010
+	movgs	gr4, dbar1	; 0x809 04011
+	movgs	gr4, dbar2	; 0x80A 04012
+	movgs	gr4, dbar3	; 0x80B 04013
+	movgs	gr4, dbdr00	; 0x80C 04014
+	movgs	gr4, dbdr01	; 0x80D 04015
+	movgs	gr4, dbdr02	; 0x80E 04016
+	movgs	gr4, dbdr03	; 0x80F 04017
+	movgs	gr4, dbdr10	; 0x810 04020
+	movgs	gr4, dbdr11	; 0x811 04021
+	movgs	gr4, dbmr00	; 0x81C 04034
+	movgs	gr4, dbmr01	; 0x81D 04035
+	movgs	gr4, dbmr10	; 0x820 04040
+	movgs	gr4, dbmr11	; 0x821 04041