cpu/

	* frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.
	(scutss): Change unit to I0.
	(calll, callil, ccalll): Add missing FR550-MAJOR and profile unit.
	(mqsaths): Fix FR400-MAJOR categorization.
	(media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc)
	(media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL.
	* frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1)
	combinations.

opcodes/
	* frv-desc.c, frv-opc.c: Regenerate.

sim/frv/
	* cache.c (frv_cache_init): Change fr400 cache statistics to match
	the fr405.
	(non_cache_access): Add missing breaks.
	* interrupts.c (set_exception_status_registers): Always set EAR15
	for data_access_errors.
	* memory.c (fr400_check_write_address): Remove redundant alignment
	check.
	* model.c: Regenerate.

11 files changed, 100 insertions, 93 deletions

diff --git a/cpu/ChangeLog b/cpu/ChangeLog
index 942f8342418..33ef3984a15 100644
--- a/cpu/ChangeLog
+++ b/cpu/ChangeLog
@@ -1,5 +1,16 @@
 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 
+	* frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.
+	(scutss): Change unit to I0.
+	(calll, callil, ccalll): Add missing FR550-MAJOR and profile unit.
+	(mqsaths): Fix FR400-MAJOR categorization.
+	(media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc)
+	(media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL.
+	* frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1)
+	combinations.
+
+2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
+
 	* frv.cpu (r-store, r-store-dual, r-store-quad): Delete.
 	(rstb, rsth, rst, rstd, rstq): Delete.
 	(rstbf, rsthf, rstf, rstdf, rstqf): Delete.
diff --git a/cpu/frv.cpu b/cpu/frv.cpu
index 238575ff55f..77254ed66c4 100644
--- a/cpu/frv.cpu
+++ b/cpu/frv.cpu
@@ -3032,8 +3032,7 @@
 	       (c-call VOID "@cpu@_signed_integer_divide"
 		       GRi GRj (index-of GRk) 1)
 	       (clobber GRk))
-     ((fr400 (unit u-idiv))
-      (fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
+     ((fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
 )
 
 (dni udiv
@@ -3059,8 +3058,7 @@
 	       (c-call VOID "@cpu@_unsigned_integer_divide"
 		       GRi GRj (index-of GRk) 1)
 	       (clobber GRk))
-     ((fr400 (unit u-idiv))
-      (fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
+     ((fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
 )
 
 ; Multiplication
@@ -3158,7 +3156,7 @@
 
 (dni scutss
      "Integer accumulator cut with saturation"
-     ((UNIT IALL) (FR400-MAJOR I-1) (MACH fr400))
+     ((UNIT I0) (FR400-MAJOR I-1) (MACH fr400))
      "scutss$pack $GRj,$GRk"
      (+ pack GRk OP_46 (rs-null) OPE1_04 GRj)
      (set GRk (c-call SI "@cpu@_iacc_cut" (reg h-iacc0 0) GRj))
@@ -3562,8 +3560,7 @@
 	       (c-call VOID "@cpu@_signed_integer_divide"
 		       GRi s12 (index-of GRk) 1)
 	       (clobber GRk))
-     ((fr400 (unit u-idiv))
-      (fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
+     ((fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
 )
 
 (dni udivi
@@ -3589,8 +3586,7 @@
 	       (c-call VOID "@cpu@_unsigned_integer_divide"
 		       GRi s12 (index-of GRk) 1)
 	       (clobber GRk))
-     ((fr400 (unit u-idiv))
-      (fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
+     ((fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
 )
 
 (define-pmacro (multiply-r-simm name signop op comment)
@@ -5537,12 +5533,12 @@
 
 (dni calll
      "call and link"
-     ((UNIT I0) (FR500-MAJOR I-5) (FR400-MAJOR I-5))
+     ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) (FR400-MAJOR I-5))
      "calll$pack @($GRi,$GRj)"
      (+ pack (misc-null-1) (LI-on) OP_0C GRi (misc-null-2) GRj)
      (jump-and-link-semantics GRi GRj LI)
      ((fr400 (unit u-branch))
-      (fr500 (unit u-branch)))
+      (fr500 (unit u-branch)) (fr550 (unit u-branch)))
 )
 
 (dni jmpil
@@ -5557,12 +5553,12 @@
 
 (dni callil
      "call immediate and link"
-     ((UNIT I0) (FR500-MAJOR I-5) (FR400-MAJOR I-5))
+     ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) (FR400-MAJOR I-5))
      "callil$pack @($GRi,$s12)"
      (+ pack (misc-null-1) (LI-on) OP_0D GRi s12)
      (jump-and-link-semantics GRi s12 LI)
      ((fr400 (unit u-branch))
-      (fr500 (unit u-branch)))
+      (fr500 (unit u-branch)) (fr550 (unit u-branch)))
 )
 
 (dni call
@@ -6084,7 +6080,8 @@
 
 (dni cjmpl
      "conditional jump and link"
-     ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) (FR400-MAJOR I-5) CONDITIONAL)
+     ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6)
+      (FR400-MAJOR I-5) CONDITIONAL)
      "cjmpl$pack @($GRi,$GRj),$CCi,$cond"
      (+ pack (misc-null-1) (LI-off) OP_6A GRi CCi cond OPE4_2 GRj)
      (if (eq CCi (or cond 2))
@@ -6095,13 +6092,14 @@
 
 (dni ccalll
      "conditional call and link"
-     ((UNIT I0) (FR500-MAJOR I-5) (FR400-MAJOR I-5) CONDITIONAL)
+     ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6)
+      (FR400-MAJOR I-5) CONDITIONAL)
      "ccalll$pack @($GRi,$GRj),$CCi,$cond"
      (+ pack (misc-null-1) (LI-on) OP_6A GRi CCi cond OPE4_2 GRj)
      (if (eq CCi (or cond 2))
 	 (jump-and-link-semantics GRi GRj LI))
      ((fr400 (unit u-branch))
-      (fr500 (unit u-branch)))
+      (fr500 (unit u-branch)) (fr550 (unit u-branch)))
 )
 
 (define-pmacro (cache-invalidate name cache all op ope profile comment)
@@ -7379,7 +7377,7 @@
 
 (dni mqsaths
      "Media quad saturation signed"
-     ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-2) (FR400-MAJOR M-1))
+     ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-2) (FR400-MAJOR M-2))
      "mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven"
      (+ pack FRintkeven OP_78 FRintieven OPE1_0F FRintjeven)
      (if (orif (register-unaligned FRintieven 2)
@@ -8060,7 +8058,7 @@
 		name mode conv addop rhw res max min op ope comment)
   (dni name
        (comment)
-       ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
+       ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
        (.str name "$pack $FRintieven,$FRintjeven,$" res)
        (+ pack res op FRintieven ope FRintjeven)
        (media-quad-multiply-cross-acc-semantics 1 mode conv addop rhw res
@@ -8110,7 +8108,7 @@
 		name mode conv addop rhw res max min op ope comment)
   (dni name
        (comment)
-       ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
+       ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
        (.str name "$pack $FRintieven,$FRintjeven,$" res)
        (+ pack res op FRintieven ope FRintjeven)
        (media-quad-cross-multiply-cross-acc-semantics 1 mode conv addop rhw res
@@ -8160,7 +8158,7 @@
 		name mode conv addop rhw res max min op ope comment)
   (dni name
        (comment)
-       ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
+       ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
        (.str name "$pack $FRintieven,$FRintjeven,$" res)
        (+ pack res op FRintieven ope FRintjeven)
        (media-quad-cross-multiply-acc-semantics 1 mode conv addop rhw res
diff --git a/cpu/frv.opc b/cpu/frv.opc
index 03c0f3e1437..e4b96575db6 100644
--- a/cpu/frv.opc
+++ b/cpu/frv.opc
@@ -499,6 +499,8 @@ fr400_check_insn_major_constraints (
     case FR400_MAJOR_M_2:
       return ! find_major_in_vliw (vliw, FR400_MAJOR_M_1)
 	&&   ! find_major_in_vliw (vliw, FR400_MAJOR_M_2);
+    case FR400_MAJOR_M_1:
+      return !find_major_in_vliw (vliw, FR400_MAJOR_M_2);
     default:
       break;
     }
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 912174daa35..85a9095d9f3 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,9 @@
 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 
+	* frv-desc.c, frv-opc.c: Regenerate.
+
+2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
+
 	* frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 
 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
diff --git a/opcodes/frv-desc.c b/opcodes/frv-desc.c
index f7eebfcdb18..083536105c0 100644
--- a/opcodes/frv-desc.c
+++ b/opcodes/frv-desc.c
@@ -2433,7 +2433,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
 /* scutss$pack $GRj,$GRk */
   {
     FRV_INSN_SCUTSS, "scutss", "scutss", 32,
-    { 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400), UNIT_I0, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
   },
 /* scan$pack $GRi,$GRj,$GRk */
   {
@@ -4128,7 +4128,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
 /* calll$pack @($GRi,$GRj) */
   {
     FRV_INSN_CALLL, "calll", "calll", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_NONE } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
   },
 /* jmpil$pack @($GRi,$s12) */
   {
@@ -4138,7 +4138,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
 /* callil$pack @($GRi,$s12) */
   {
     FRV_INSN_CALLIL, "callil", "callil", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_NONE } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
   },
 /* call$pack $label24 */
   {
@@ -4863,7 +4863,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
 /* ccalll$pack @($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CCALLL, "ccalll", "ccalll", 32,
-    { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_NONE } }
+    { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
   },
 /* ici$pack @($GRi,$GRj) */
   {
@@ -5578,7 +5578,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
 /* mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MQSATHS, "mqsaths", "mqsaths", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } }
   },
 /* msathu$pack $FRinti,$FRintj,$FRintk */
   {
@@ -5823,17 +5823,17 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
 /* mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQXMACHS, "mqxmachs", "mqxmachs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
 /* mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQXMACXHS, "mqxmacxhs", "mqxmacxhs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
 /* mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQMACXHS, "mqmacxhs", "mqmacxhs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
 /* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
   {
diff --git a/opcodes/frv-opc.c b/opcodes/frv-opc.c
index f1b1127cef1..2865f7297dd 100644
--- a/opcodes/frv-opc.c
+++ b/opcodes/frv-opc.c
@@ -453,6 +453,8 @@ fr400_check_insn_major_constraints (
     case FR400_MAJOR_M_2:
       return ! find_major_in_vliw (vliw, FR400_MAJOR_M_1)
 	&&   ! find_major_in_vliw (vliw, FR400_MAJOR_M_2);
+    case FR400_MAJOR_M_1:
+      return !find_major_in_vliw (vliw, FR400_MAJOR_M_2);
     default:
       break;
     }
diff --git a/sim/frv/ChangeLog b/sim/frv/ChangeLog
index 652c956fb27..73a6a84b90f 100644
--- a/sim/frv/ChangeLog
+++ b/sim/frv/ChangeLog
@@ -1,5 +1,16 @@
 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 
+	* cache.c (frv_cache_init): Change fr400 cache statistics to match
+	the fr405.
+	(non_cache_access): Add missing breaks.
+	* interrupts.c (set_exception_status_registers): Always set EAR15
+	for data_access_errors.
+	* memory.c (fr400_check_write_address): Remove redundant alignment
+	check.
+	* model.c: Regenerate.
+
+2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
+
 	* frv.c (frvbf_iacc_cut): Rework, taking rounding into account.
 
 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
diff --git a/sim/frv/cache.c b/sim/frv/cache.c
index 7b2635b6d26..578a01141a8 100644
--- a/sim/frv/cache.c
+++ b/sim/frv/cache.c
@@ -39,7 +39,7 @@ frv_cache_init (SIM_CPU *cpu, FRV_CACHE *cache)
     {
     case bfd_mach_fr400:
       if (cache->configured_sets == 0)
-	cache->configured_sets = 128;
+	cache->configured_sets = 512;
       if (cache->configured_ways == 0)
 	cache->configured_ways = 2;
       if (cache->line_size == 0)
@@ -208,6 +208,7 @@ non_cache_access (FRV_CACHE *cache, USI address)
       if (address >= 0xff000000
 	  || address >= 0xfe000000 && address <= 0xfeffffff)
 	return 1; /* non-cache access */
+      break;
     case bfd_mach_fr550:
       if (address >= 0xff000000
 	  || address >= 0xfeff0000 && address <= 0xfeffffff)
@@ -219,6 +220,7 @@ non_cache_access (FRV_CACHE *cache, USI address)
 	}
       else if (address >= 0xfe400000 && address <= 0xfe407fff)
 	return 1; /* non-cache access */
+      break;
     default:
       if (address >= 0xff000000
 	  || address >= 0xfeff0000 && address <= 0xfeffffff)
@@ -230,6 +232,7 @@ non_cache_access (FRV_CACHE *cache, USI address)
 	}
       else if (address >= 0xfe400000 && address <= 0xfe403fff)
 	return 1; /* non-cache access */
+      break;
     }
 
   hsr0 = GET_HSR0 ();
diff --git a/sim/frv/interrupts.c b/sim/frv/interrupts.c
index 540ee06e28d..1496fc558f5 100644
--- a/sim/frv/interrupts.c
+++ b/sim/frv/interrupts.c
@@ -845,8 +845,7 @@ set_exception_status_registers (
 	  break;
 	case FRV_DATA_ACCESS_ERROR:
 	  reg_index = 15; /* Use ESR15, EPCR15.  */
-	  if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr400)
-	    set_ear = 1;
+	  set_ear = 1;
 	  break;
 	case FRV_DATA_ACCESS_EXCEPTION:
 	  set_daec = 1;
diff --git a/sim/frv/memory.c b/sim/frv/memory.c
index 4dbc65242ac..adee4c15a90 100644
--- a/sim/frv/memory.c
+++ b/sim/frv/memory.c
@@ -679,18 +679,6 @@ frvbf_read_imem_USI (SIM_CPU *current_cpu, PCADDR vpc)
 static SI
 fr400_check_write_address (SIM_CPU *current_cpu, SI address, int align_mask)
 {
-  if (address & align_mask)
-    {
-      /* On the fr400, this causes a data_access_error.  */
-      /* Make sure that this exception is not masked.  */
-      USI isr = GET_ISR ();
-      if (! GET_ISR_EMAM (isr))
-	{
-	  /* Bad alignment causes a data_access_error on fr400.  */
-	  frv_queue_data_access_error_interrupt (current_cpu, address);
-	}
-      address &= ~align_mask;
-    }
   if (align_mask == 7
       && address >= 0xfe800000 && address <= 0xfeffffff)
     frv_queue_program_interrupt (current_cpu, FRV_DATA_STORE_ERROR);
diff --git a/sim/frv/model.c b/sim/frv/model.c
index 14c268b3b05..0fa5d4b3ab9 100644
--- a/sim/frv/model.c
+++ b/sim/frv/model.c
@@ -20263,7 +20263,16 @@ model_fr550_calll (SIM_CPU *current_cpu, void *sem_arg)
   {
     int referenced = 0;
     int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
   }
   return cycles;
 #undef FLD
@@ -20302,7 +20311,14 @@ model_fr550_callil (SIM_CPU *current_cpu, void *sem_arg)
   {
     int referenced = 0;
     int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    referenced |= 1 << 0;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
   }
   return cycles;
 #undef FLD
@@ -23424,7 +23440,16 @@ model_fr550_ccalll (SIM_CPU *current_cpu, void *sem_arg)
   {
     int referenced = 0;
     int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
   }
   return cycles;
 #undef FLD
@@ -57775,17 +57800,7 @@ model_fr400_nsdiv (SIM_CPU *current_cpu, void *sem_arg)
   {
     int referenced = 0;
     int UNUSED insn_referenced = abuf->written;
-    INT in_GRi = -1;
-    INT in_GRj = -1;
-    INT out_GRk = -1;
-    INT out_ICCi_1 = -1;
-    in_GRi = FLD (in_GRi);
-    in_GRj = FLD (in_GRj);
-    out_GRk = FLD (out_GRk);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
   }
   return cycles;
 #undef FLD
@@ -57827,17 +57842,7 @@ model_fr400_nudiv (SIM_CPU *current_cpu, void *sem_arg)
   {
     int referenced = 0;
     int UNUSED insn_referenced = abuf->written;
-    INT in_GRi = -1;
-    INT in_GRj = -1;
-    INT out_GRk = -1;
-    INT out_ICCi_1 = -1;
-    in_GRi = FLD (in_GRi);
-    in_GRj = FLD (in_GRj);
-    out_GRk = FLD (out_GRk);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
   }
   return cycles;
 #undef FLD
@@ -59267,15 +59272,7 @@ model_fr400_nsdivi (SIM_CPU *current_cpu, void *sem_arg)
   {
     int referenced = 0;
     int UNUSED insn_referenced = abuf->written;
-    INT in_GRi = -1;
-    INT in_GRj = -1;
-    INT out_GRk = -1;
-    INT out_ICCi_1 = -1;
-    in_GRi = FLD (in_GRi);
-    out_GRk = FLD (out_GRk);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
   }
   return cycles;
 #undef FLD
@@ -59315,15 +59312,7 @@ model_fr400_nudivi (SIM_CPU *current_cpu, void *sem_arg)
   {
     int referenced = 0;
     int UNUSED insn_referenced = abuf->written;
-    INT in_GRi = -1;
-    INT in_GRj = -1;
-    INT out_GRk = -1;
-    INT out_ICCi_1 = -1;
-    in_GRi = FLD (in_GRi);
-    out_GRk = FLD (out_GRk);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
   }
   return cycles;
 #undef FLD
@@ -86433,9 +86422,9 @@ static const INSN_TIMING fr550_timing[] = {
   { FRVBF_INSN_FCBULR, model_fr550_fcbulr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
   { FRVBF_INSN_FCBOLR, model_fr550_fcbolr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
   { FRVBF_INSN_JMPL, model_fr550_jmpl, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
-  { FRVBF_INSN_CALLL, model_fr550_calll, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CALLL, model_fr550_calll, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
   { FRVBF_INSN_JMPIL, model_fr550_jmpil, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
-  { FRVBF_INSN_CALLIL, model_fr550_callil, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CALLIL, model_fr550_callil, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
   { FRVBF_INSN_CALL, model_fr550_call, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
   { FRVBF_INSN_RETT, model_fr550_rett, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_REI, model_fr550_rei, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
@@ -86580,7 +86569,7 @@ static const INSN_TIMING fr550_timing[] = {
   { FRVBF_INSN_CFCKU, model_fr550_cfcku, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
   { FRVBF_INSN_CFCKO, model_fr550_cfcko, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
   { FRVBF_INSN_CJMPL, model_fr550_cjmpl, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
-  { FRVBF_INSN_CCALLL, model_fr550_ccalll, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCALLL, model_fr550_ccalll, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
   { FRVBF_INSN_ICI, model_fr550_ici, { { (int) UNIT_FR550_U_ICI, 1, 1 } } },
   { FRVBF_INSN_DCI, model_fr550_dci, { { (int) UNIT_FR550_U_DCI, 1, 1 } } },
   { FRVBF_INSN_ICEI, model_fr550_icei, { { (int) UNIT_FR550_U_ICI, 1, 1 } } },
@@ -88323,9 +88312,9 @@ static const INSN_TIMING fr400_timing[] = {
   { FRVBF_INSN_XOR, model_fr400_xor, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
   { FRVBF_INSN_NOT, model_fr400_not, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
   { FRVBF_INSN_SDIV, model_fr400_sdiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
-  { FRVBF_INSN_NSDIV, model_fr400_nsdiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_NSDIV, model_fr400_nsdiv, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_UDIV, model_fr400_udiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
-  { FRVBF_INSN_NUDIV, model_fr400_nudiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_NUDIV, model_fr400_nudiv, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_SMUL, model_fr400_smul, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
   { FRVBF_INSN_UMUL, model_fr400_umul, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
   { FRVBF_INSN_SMU, model_fr400_smu, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
@@ -88381,9 +88370,9 @@ static const INSN_TIMING fr400_timing[] = {
   { FRVBF_INSN_ORI, model_fr400_ori, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
   { FRVBF_INSN_XORI, model_fr400_xori, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
   { FRVBF_INSN_SDIVI, model_fr400_sdivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
-  { FRVBF_INSN_NSDIVI, model_fr400_nsdivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_NSDIVI, model_fr400_nsdivi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_UDIVI, model_fr400_udivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
-  { FRVBF_INSN_NUDIVI, model_fr400_nudivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_NUDIVI, model_fr400_nudivi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_SMULI, model_fr400_smuli, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
   { FRVBF_INSN_UMULI, model_fr400_umuli, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
   { FRVBF_INSN_SLLI, model_fr400_slli, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },