gas: blackfin: reject invalid register destinations for vector add/sub

The destination registers with vector add/sub insns must be different,
so make sure gas rejects attempt to write these.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

5 files changed, 30 insertions, 1 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 4c4a03c4aad..61478ffe405 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,12 @@
 2011-03-24  Mike Frysinger  <vapier@gentoo.org>
 
+	* config/bfin-parse.y (dual 32bit add/sub): Return yyerror when dest
+	reg $1 is the same as dest reg $7.
+	(quad 16bit add/sub): Return yyerror when dest reg $1 is the same as
+	dest reg $7.
+
+2011-03-24  Mike Frysinger  <vapier@gentoo.org>
+
 	* config/bfin-parse.y (check_macfuncs): Clarify error message when
 	P is mismatched.  Check destination regno are off by one when P is
 	set, or are equal when P is not set.
diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y
index f20d20b3c18..803afd1c552 100644
--- a/gas/config/bfin-parse.y
+++ b/gas/config/bfin-parse.y
@@ -1,5 +1,5 @@
 /* bfin-parse.y  ADI Blackfin parser
-   Copyright 2005, 2006, 2007, 2008, 2009, 2010
+   Copyright 2005, 2006, 2007, 2008, 2009, 2010, 2011
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -898,6 +898,9 @@ asm_1:
 
 	| REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
 	{
+	  if (REG_SAME ($1, $7))
+	    return yyerror ("Resource conflict in dest reg");
+
 	  if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
 	      && IS_A1 ($9) && !IS_A1 ($11))
 	    {
@@ -941,6 +944,8 @@ asm_1:
 	  if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7))
 	    return yyerror ("Dregs expected");
 
+	  if (REG_SAME ($1, $7))
+	    return yyerror ("Resource conflict in dest reg");
 
 	  if ($4.r0 == 1 && $10.r0 == 2)
 	    {
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index ce01151d76d..7975fb851f9 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,5 +1,10 @@
 2011-03-24  Mike Frysinger  <vapier@gentoo.org>
 
+	* gas/bfin/expected_errors.s: Add invalid vector add/sub insn tests.
+	* gas/bfin/expected_errors.l: Add new error messages.
+
+2011-03-24  Mike Frysinger  <vapier@gentoo.org>
+
 	* gas/bfin/16bit_illegals.d, gas/bfin/16bit_illegals.s: Delete.
 	* gas/bfin/allinsn16.d, gas/bfin/allinsn16.s: New files.
 	* gas/bfin/bfin.exp: Change 16bit_illegals to allinsn16.
diff --git a/gas/testsuite/gas/bfin/expected_errors.l b/gas/testsuite/gas/bfin/expected_errors.l
index 316ff20f661..863b30bdadc 100644
--- a/gas/testsuite/gas/bfin/expected_errors.l
+++ b/gas/testsuite/gas/bfin/expected_errors.l
@@ -95,3 +95,8 @@
 .*:120: Error: Destination Dregs \(full\) must differ by one.
 .*:121: Error: Destination Dregs \(half\) must match.
 .*:122: Error: Destination Dreg sizes \(full or half\) must match.
+.*:124: Error: Resource conflict in dest reg.
+.*:125: Error: Differing source registers.
+.*:126: Error: Resource conflict in dest reg.
+.*:127: Error: Differing source registers.
+.*:129: Error: Register mismatch.
diff --git a/gas/testsuite/gas/bfin/expected_errors.s b/gas/testsuite/gas/bfin/expected_errors.s
index 736613ff720..46be66c3a47 100644
--- a/gas/testsuite/gas/bfin/expected_errors.s
+++ b/gas/testsuite/gas/bfin/expected_errors.s
@@ -120,3 +120,10 @@
 	R0 = A0, R3 = A1;
 	R0.L = A0, R1.H = A1;
 	R0 = A0, R1.H = A1;
+
+	R0 = R1 +|+ R2, R0 = R1 -|- R2;
+	R0 = R4 +|+ R5, R1 = R6 -|- R7;
+	R1 = R3 +|- R7, R1 = R3 -|+ R7;
+	R7 = R3 +|- R4, R1 = R1 -|+ R2;
+
+	R0 = R3 + R4, R1 = R5 - R6;