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authorJan Beulich <jbeulich@novell.com>2014-10-21 09:56:38 +0200
committerAlan Modra <amodra@gmail.com>2014-10-28 16:54:37 +1030
commit2609fe3d3f84ce62b373daa56ba615465c2d5293 (patch)
tree30f3f9f233c99793c77be4df703d15076b29f185
parent334efb9a97018d8b2f508e5c22e5acb7b824cc76 (diff)
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ppc: enable msgclr and msgsnd on Power8
According to my reading of the spec it was an oversight for them to not having got enabled when Power8 support got added.
-rw-r--r--gas/testsuite/ChangeLog4
-rw-r--r--gas/testsuite/gas/ppc/power8.d2
-rw-r--r--gas/testsuite/gas/ppc/power8.s2
-rw-r--r--opcodes/ChangeLog6
-rw-r--r--opcodes/ppc-opc.c4
5 files changed, 16 insertions, 2 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 1e9d7efd9e6..b391709ed7f 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,6 +1,10 @@
2014-10-28 Alan Modra <amodra@gmail.com>
Apply truck patches
+ 2014-10-21 Jan Beulich <jbeulich@suse.com>
+ * gas/ppc/power8.s: Test msgclr and msgsnd.
+ * gas/ppc/power8.d: Adjust accordingly.
+
2014-10-18 Alan Modra <amodra@gmail.com>
* gas/i386/inval-equ-2.l: Adjust.
diff --git a/gas/testsuite/gas/ppc/power8.d b/gas/testsuite/gas/ppc/power8.d
index 2d576e6f3db..e66951e2100 100644
--- a/gas/testsuite/gas/ppc/power8.d
+++ b/gas/testsuite/gas/ppc/power8.d
@@ -150,4 +150,6 @@ Disassembly of section \.text:
230: (f3 60 d5 2d|2d d5 60 f3) xscvspdpn vs59,vs26
234: (ff 0e 16 8c|8c 16 0e ff) fmrgow f24,f14,f2
238: (fe c7 2f 8c|8c 2f c7 fe) fmrgew f22,f7,f5
+ 23c: (7c 00 71 9c|9c 71 00 7c) msgsnd r14
+ 240: (7c 00 b9 dc|dc b9 00 7c) msgclr r23
#pass
diff --git a/gas/testsuite/gas/ppc/power8.s b/gas/testsuite/gas/ppc/power8.s
index 8df4f6b20e9..09dbe43c38b 100644
--- a/gas/testsuite/gas/ppc/power8.s
+++ b/gas/testsuite/gas/ppc/power8.s
@@ -142,3 +142,5 @@ power8:
xscvspdpn 59,26
fmrgow 24,14,2
fmrgew 22,7,5
+ msgsnd 14
+ msgclr 23
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a8fa3423ce8..cdb3a993778 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2014-10-28 Alan Modra <amodra@gmail.com>
+
+ Apply trunk patches
+ 2014-10-21 Jan Beulich <jbeulich@suse.com>
+ * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
+
2014-10-15 Tristan Gingold <gingold@adacore.com>
* configure: Regenerate.
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index a5cfe1aab25..bcc0ca0d837 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4653,7 +4653,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}},
+{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}},
{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
@@ -4700,7 +4700,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
-{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}},
+{"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}},
{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},