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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020 MediaTek Inc.
*
* Author: Weijie Gao <weijie.gao@mediatek.com>
*/
#ifndef __CONFIG_MT7628_H
#define __CONFIG_MT7628_H
#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_OFFSET 0x80000
#define CONFIG_SYS_BOOTM_LEN 0x1000000
/* Serial SPL */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_NS16550_CLK 40000000
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM1 0xb0000c00
#endif
/* Serial common */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600 }
/* SPL */
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SPL_BSS_START_ADDR 0x80010000
#define CONFIG_SPL_BSS_MAX_SIZE 0x10000
/* Dummy value */
#define CONFIG_SYS_UBOOT_BASE 0
#endif /* __CONFIG_MT7628_H */
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