1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
|
/*
* (C) Copyright 2017
* Vikas Manocha, <vikas.manocha@st.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <ram.h>
#include <asm/io.h>
#include <asm/arch/fmc.h>
#include <asm/arch/stm32.h>
DECLARE_GLOBAL_DATA_PTR;
struct stm32_sdram_control {
u8 no_columns;
u8 no_rows;
u8 memory_width;
u8 no_banks;
u8 cas_latency;
u8 sdclk;
u8 rd_burst;
u8 rd_pipe_delay;
};
struct stm32_sdram_timing {
u8 tmrd;
u8 txsr;
u8 tras;
u8 trc;
u8 trp;
u8 twr;
u8 trcd;
};
struct stm32_sdram_params {
u8 no_sdram_banks;
struct stm32_sdram_control sdram_control;
struct stm32_sdram_timing sdram_timing;
u32 sdram_ref_count;
};
#define SDRAM_MODE_BL_SHIFT 0
#define SDRAM_MODE_CAS_SHIFT 4
#define SDRAM_MODE_BL 0
int stm32_sdram_init(struct udevice *dev)
{
struct stm32_sdram_params *params = dev_get_platdata(dev);
writel(params->sdram_control.sdclk << FMC_SDCR_SDCLK_SHIFT
| params->sdram_control.cas_latency << FMC_SDCR_CAS_SHIFT
| params->sdram_control.no_banks << FMC_SDCR_NB_SHIFT
| params->sdram_control.memory_width << FMC_SDCR_MWID_SHIFT
| params->sdram_control.no_rows << FMC_SDCR_NR_SHIFT
| params->sdram_control.no_columns << FMC_SDCR_NC_SHIFT
| params->sdram_control.rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
| params->sdram_control.rd_burst << FMC_SDCR_RBURST_SHIFT,
&STM32_SDRAM_FMC->sdcr1);
writel(params->sdram_timing.trcd << FMC_SDTR_TRCD_SHIFT
| params->sdram_timing.trp << FMC_SDTR_TRP_SHIFT
| params->sdram_timing.twr << FMC_SDTR_TWR_SHIFT
| params->sdram_timing.trc << FMC_SDTR_TRC_SHIFT
| params->sdram_timing.tras << FMC_SDTR_TRAS_SHIFT
| params->sdram_timing.txsr << FMC_SDTR_TXSR_SHIFT
| params->sdram_timing.tmrd << FMC_SDTR_TMRD_SHIFT,
&STM32_SDRAM_FMC->sdtr1);
writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
&STM32_SDRAM_FMC->sdcmr);
udelay(200); /* 200 us delay, page 10, "Power-Up" */
FMC_BUSY_WAIT();
writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
&STM32_SDRAM_FMC->sdcmr);
udelay(100);
FMC_BUSY_WAIT();
writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
| 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
udelay(100);
FMC_BUSY_WAIT();
writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
| params->sdram_control.cas_latency << SDRAM_MODE_CAS_SHIFT)
<< FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
&STM32_SDRAM_FMC->sdcmr);
udelay(100);
FMC_BUSY_WAIT();
writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
&STM32_SDRAM_FMC->sdcmr);
FMC_BUSY_WAIT();
/* Refresh timer */
writel((params->sdram_ref_count) << 1, &STM32_SDRAM_FMC->sdrtr);
return 0;
}
static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
{
int ret;
int node = dev->of_offset;
const void *blob = gd->fdt_blob;
struct stm32_sdram_params *params = dev_get_platdata(dev);
params->no_sdram_banks = fdtdec_get_uint(blob, node, "mr-nbanks", 1);
debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
fdt_for_each_subnode(node, blob, node) {
ret = fdtdec_get_byte_array(blob, node, "st,sdram-control",
(u8 *)¶ms->sdram_control,
sizeof(params->sdram_control));
if (ret)
return ret;
ret = fdtdec_get_byte_array(blob, node, "st,sdram-timing",
(u8 *)¶ms->sdram_timing,
sizeof(params->sdram_timing));
if (ret)
return ret;
params->sdram_ref_count = fdtdec_get_int(blob, node,
"st,sdram-refcount", 8196);
}
return 0;
}
static int stm32_fmc_probe(struct udevice *dev)
{
#ifdef CONFIG_CLK
int ret;
struct clk clk;
ret = clk_get_by_index(dev, 0, &clk);
if (ret < 0)
return ret;
ret = clk_enable(&clk);
if (ret) {
dev_err(dev, "failed to enable clock\n");
return ret;
}
#endif
ret = stm32_sdram_init(dev);
if (ret)
return ret;
return 0;
}
static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info)
{
return 0;
}
static struct ram_ops stm32_fmc_ops = {
.get_info = stm32_fmc_get_info,
};
static const struct udevice_id stm32_fmc_ids[] = {
{ .compatible = "st,stm32-fmc" },
{ }
};
U_BOOT_DRIVER(stm32_fmc) = {
.name = "stm32_fmc",
.id = UCLASS_RAM,
.of_match = stm32_fmc_ids,
.ops = &stm32_fmc_ops,
.ofdata_to_platdata = stm32_fmc_ofdata_to_platdata,
.probe = stm32_fmc_probe,
.platdata_auto_alloc_size = sizeof(struct stm32_sdram_params),
};
|
