1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
|
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2014
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Basic support for the pwm module on imx6.
*/
#include <common.h>
#include <div64.h>
#include <dm.h>
#include <log.h>
#include <pwm.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include "pwm-imx-util.h"
int pwm_init(int pwm_id, int div, int invert)
{
struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
if (!pwm)
return -1;
writel(0, &pwm->ir);
return 0;
}
int pwm_config_internal(struct pwm_regs *pwm, unsigned long period_cycles,
unsigned long duty_cycles, unsigned long prescale)
{
u32 cr;
writel(0, &pwm->ir);
cr = PWMCR_PRESCALER(prescale) |
PWMCR_DOZEEN | PWMCR_WAITEN |
PWMCR_DBGEN | PWMCR_CLKSRC_IPG_HIGH;
writel(cr, &pwm->cr);
/* set duty cycles */
writel(duty_cycles, &pwm->sar);
/* set period cycles */
writel(period_cycles, &pwm->pr);
return 0;
}
int pwm_config(int pwm_id, int duty_ns, int period_ns)
{
struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
unsigned long period_cycles, duty_cycles, prescale;
if (!pwm)
return -1;
pwm_imx_get_parms(period_ns, duty_ns, &period_cycles, &duty_cycles,
&prescale);
return pwm_config_internal(pwm, period_cycles, duty_cycles, prescale);
}
int pwm_enable(int pwm_id)
{
struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
if (!pwm)
return -1;
setbits_le32(&pwm->cr, PWMCR_EN);
return 0;
}
void pwm_disable(int pwm_id)
{
struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
if (!pwm)
return;
clrbits_le32(&pwm->cr, PWMCR_EN);
}
#if defined(CONFIG_DM_PWM)
struct imx_pwm_priv {
struct pwm_regs *regs;
bool invert;
};
static int imx_pwm_set_invert(struct udevice *dev, uint channel,
bool polarity)
{
struct imx_pwm_priv *priv = dev_get_priv(dev);
debug("%s: polarity=%u\n", __func__, polarity);
priv->invert = polarity;
return 0;
}
static int imx_pwm_set_config(struct udevice *dev, uint channel,
uint period_ns, uint duty_ns)
{
struct imx_pwm_priv *priv = dev_get_priv(dev);
struct pwm_regs *regs = priv->regs;
unsigned long period_cycles, duty_cycles, prescale;
debug("%s: Config '%s' channel: %d\n", __func__, dev->name, channel);
pwm_imx_get_parms(period_ns, duty_ns, &period_cycles, &duty_cycles,
&prescale);
return pwm_config_internal(regs, period_cycles, duty_cycles, prescale);
};
static int imx_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
{
struct imx_pwm_priv *priv = dev_get_priv(dev);
struct pwm_regs *regs = priv->regs;
debug("%s: Enable '%s' state: %d\n", __func__, dev->name, enable);
if (enable)
setbits_le32(®s->cr, PWMCR_EN);
else
clrbits_le32(®s->cr, PWMCR_EN);
return 0;
};
static int imx_pwm_ofdata_to_platdata(struct udevice *dev)
{
struct imx_pwm_priv *priv = dev_get_priv(dev);
priv->regs = (struct pwm_regs *)devfdt_get_addr(dev);
return 0;
}
static int imx_pwm_probe(struct udevice *dev)
{
return 0;
}
static const struct pwm_ops imx_pwm_ops = {
.set_invert = imx_pwm_set_invert,
.set_config = imx_pwm_set_config,
.set_enable = imx_pwm_set_enable,
};
static const struct udevice_id imx_pwm_ids[] = {
{ .compatible = "fsl,imx27-pwm" },
{ }
};
U_BOOT_DRIVER(imx_pwm) = {
.name = "imx_pwm",
.id = UCLASS_PWM,
.of_match = imx_pwm_ids,
.ops = &imx_pwm_ops,
.ofdata_to_platdata = imx_pwm_ofdata_to_platdata,
.probe = imx_pwm_probe,
.priv_auto_alloc_size = sizeof(struct imx_pwm_priv),
};
#endif
|
