blob: 707be7779eb094f29e2920ab1f53ce43620bd92d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
|
// SPDX-License-Identifier: GPL-2.0+
/*
* T30 QC750 SPL stage configuration
*
* (C) Copyright 2010-2013
* NVIDIA Corporation <www.nvidia.com>
*
* (C) Copyright 2023
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>
#define MAX77663_I2C_ADDR (0x3c << 1)
#define MAX77663_REG_SD0 0x16
#define MAX77663_REG_SD0_DATA (0x2100 | MAX77663_REG_SD0)
#define MAX77663_REG_SD1 0x17
#define MAX77663_REG_SD1_DATA (0x3000 | MAX77663_REG_SD1)
#define MAX77663_REG_LDO4 0x2b
#define MAX77663_REG_LDO4_DATA (0xE000 | MAX77663_REG_LDO4)
#define MAX77663_REG_GPIO4 0x3a
#define MAX77663_REG_GPIO4_DATA (0x0100 | MAX77663_REG_GPIO4)
void pmic_enable_cpu_vdd(void)
{
/* Set VDD_CORE to 1.200V. */
tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD1_DATA);
udelay(1000);
/* Bring up VDD_CPU to 1.0125V. */
tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD0_DATA);
udelay(1000);
/* Bring up VDD_RTC to 1.200V. */
tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_LDO4_DATA);
udelay(10 * 1000);
/* Set 32k-out gpio state */
tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO4_DATA);
}
|
