blob: 7e9aac80ff60f8a5041860b8f93746b31732ce1c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
|
/*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_CACHE_H
#define _ASM_CACHE_H
/* cache */
int icache_status(void);
void icache_enable(void);
void icache_disable(void);
int dcache_status(void);
void dcache_enable(void);
void dcache_disable(void);
void cache_flush(void);
#define DEFINE_GET_SYS_REG(reg) \
static inline unsigned long GET_##reg(void) \
{ \
unsigned long val; \
__asm__ volatile ( \
"mfsr %0, $"#reg : "=&r" (val) : : "memory" \
); \
return val; \
}
enum cache_t {ICACHE, DCACHE};
DEFINE_GET_SYS_REG(ICM_CFG);
DEFINE_GET_SYS_REG(DCM_CFG);
/* I-cache sets (# of cache lines) per way */
#define ICM_CFG_OFF_ISET 0
/* I-cache ways */
#define ICM_CFG_OFF_IWAY 3
#define ICM_CFG_MSK_ISET (0x7 << ICM_CFG_OFF_ISET)
#define ICM_CFG_MSK_IWAY (0x7 << ICM_CFG_OFF_IWAY)
/* D-cache sets (# of cache lines) per way */
#define DCM_CFG_OFF_DSET 0
/* D-cache ways */
#define DCM_CFG_OFF_DWAY 3
#define DCM_CFG_MSK_DSET (0x7 << DCM_CFG_OFF_DSET)
#define DCM_CFG_MSK_DWAY (0x7 << DCM_CFG_OFF_DWAY)
/* I-cache line size */
#define ICM_CFG_OFF_ISZ 6
#define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ)
/* D-cache line size */
#define DCM_CFG_OFF_DSZ 6
#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ)
/*
* The current upper bound for NDS32 L1 data cache line sizes is 32 bytes.
* We use that value for aligning DMA buffers unless the board config has
* specified an alternate cache line size.
*/
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#else
#define ARCH_DMA_MINALIGN 32
#endif
#endif /* _ASM_CACHE_H */
|
