path: root/arch/arm/dts/mt7988.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2022 MediaTek Inc.
 * Author: Sam Shih <sam.shih@mediatek.com>
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt7988-clk.h>
#include <dt-bindings/reset/mt7988-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>

/ {
	compatible = "mediatek,mt7988-rfb";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0>;
			mediatek,hwver = <&hwver>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x1>;
			mediatek,hwver = <&hwver>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x2>;
			mediatek,hwver = <&hwver>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x3>;
			mediatek,hwver = <&hwver>;
		};
	};

	system_clk: dummy40m {
		compatible = "fixed-clock";
		clock-frequency = <40000000>;
		#clock-cells = <0>;
	};

	spi_clk: dummy208m {
		compatible = "fixed-clock";
		clock-frequency = <208000000>;
		#clock-cells = <0>;
	};

	hwver: hwver {
		compatible = "mediatek,hwver", "syscon";
		reg = <0 0x8000000 0 0x1000>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		clock-frequency = <13000000>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	watchdog: watchdog@1001c000 {
		compatible = "mediatek,mt7622-wdt",
			     "mediatek,mt6589-wdt",
			     "syscon";
		reg = <0 0x1001c000 0 0x1000>;
		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
		#reset-cells = <1>;
	};

	gic: interrupt-controller@c000000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		interrupt-controller;
		reg = <0 0x0c000000 0 0x40000>,  /* GICD */
		      <0 0x0c080000 0 0x200000>; /* GICR */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	infracfg_ao_cgs: infracfg_ao_cgs@10001000 {
		compatible = "mediatek,mt7988-infracfg_ao_cgs", "syscon";
		reg = <0 0x10001000 0 0x1000>;
		clock-parent = <&infracfg_ao>;
		#clock-cells = <1>;
	};

	apmixedsys: apmixedsys@1001e000 {
		compatible = "mediatek,mt7988-fixed-plls", "syscon";
		reg = <0 0x1001e000 0 0x1000>;
		#clock-cells = <1>;
	};

	topckgen: topckgen@1001b000 {
		compatible = "mediatek,mt7988-topckgen", "syscon";
		reg = <0 0x1001b000 0 0x1000>;
		clock-parent = <&apmixedsys>;
		#clock-cells = <1>;
	};

	pinctrl: pinctrl@1001f000 {
		compatible = "mediatek,mt7988-pinctrl";
		reg = <0 0x1001f000 0 0x1000>,
		      <0 0x11c10000 0 0x1000>,
		      <0 0x11d00000 0 0x1000>,
		      <0 0x11d20000 0 0x1000>,
		      <0 0x11e00000 0 0x1000>,
		      <0 0x11f00000 0 0x1000>,
		      <0 0x1000b000 0 0x1000>;
		reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base",
			    "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
			    "eint";
		gpio: gpio-controller {
			gpio-controller;
			#gpio-cells = <2>;
		};
	};

	sgmiisys0: syscon@10060000 {
		compatible = "mediatek,mt7988-sgmiisys_0", "syscon";
		reg = <0 0x10060000 0 0x1000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
	};

	sgmiisys1: syscon@10070000 {
		compatible = "mediatek,mt7988-sgmiisys_1", "syscon";
		reg = <0 0x10070000 0 0x1000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
	};

	usxgmiisys0: syscon@10080000 {
		compatible = "mediatek,mt7988-usxgmiisys_0", "syscon";
		reg = <0 0x10080000 0 0x1000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
	};

	usxgmiisys1: syscon@10081000 {
		compatible = "mediatek,mt7988-usxgmiisys_1", "syscon";
		reg = <0 0x10081000 0 0x1000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
	};

	dummy_clk: dummy12m {
		compatible = "fixed-clock";
		clock-frequency = <12000000>;
		#clock-cells = <0>;
		/* must need this line, or uart uanable to get dummy_clk */
		bootph-all;
	};

	xhci1: xhci@11200000 {
		compatible = "mediatek,mt7988-xhci",
			     "mediatek,mtk-xhci";
		reg = <0 0x11200000 0 0x2e00>,
		      <0 0x11203e00 0 0x0100>;
		reg-names = "mac", "ippc";
		interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
		phys = <&tphyu2port0 PHY_TYPE_USB2>,
		       <&tphyu3port0 PHY_TYPE_USB3>;
		clocks = <&dummy_clk>,
			 <&dummy_clk>,
			 <&dummy_clk>,
			 <&dummy_clk>,
			 <&dummy_clk>;
		clock-names = "sys_ck",
			      "xhci_ck",
			      "ref_ck",
			      "mcu_ck",
			      "dma_ck";
		#address-cells = <2>;
		#size-cells = <2>;
		status = "okay";
	};

	usbtphy: usb-phy@11c50000 {
		compatible = "mediatek,mt7988",
			     "mediatek,generic-tphy-v2";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "okay";

		tphyu2port0: usb-phy@11c50000 {
			reg = <0 0x11c50000 0 0x700>;
			clocks = <&dummy_clk>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};

		tphyu3port0: usb-phy@11c50700 {
			reg = <0 0x11c50700 0 0x900>;
			clocks = <&dummy_clk>;
			clock-names = "ref";
			#phy-cells = <1>;
			mediatek,usb3-pll-ssc-delta;
			mediatek,usb3-pll-ssc-delta1;
			status = "okay";
		};
	};

	xfi_pextp0: syscon@11f20000 {
		compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
		reg = <0 0x11f20000 0 0x10000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
	};

	xfi_pextp1: syscon@11f30000 {
		compatible = "mediatek,mt7988-xfi_pextp_1", "syscon";
		reg = <0 0x11f30000 0 0x10000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
	};

	xfi_pll: syscon@11f40000 {
		compatible = "mediatek,mt7988-xfi_pll", "syscon";
		reg = <0 0x11f40000 0 0x1000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
	};

	topmisc: topmisc@11d10000 {
		compatible = "mediatek,mt7988-topmisc", "syscon",
			     "mediatek,mt7988-power-controller";
		reg = <0 0x11d10000 0 0x10000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
	};

	infracfg_ao: infracfg@10001000 {
		compatible = "mediatek,mt7988-infracfg", "syscon";
		reg = <0 0x10001000 0 0x1000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
	};

	uart0: serial@11000000 {
		compatible = "mediatek,hsuart";
		reg = <0 0x11000000 0 0x100>;
		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>;
		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
				  <&infracfg_ao CK_INFRA_MUX_UART0_SEL>;
		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
					 <&infracfg_ao CK_INFRA_UART_O0>;
		status = "disabled";
	};

	uart1: serial@11000100 {
		compatible = "mediatek,hsuart";
		reg = <0 0x11000100 0 0x100>;
		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>;
		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
				  <&infracfg_ao CK_INFRA_MUX_UART1_SEL>;
		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
					 <&infracfg_ao CK_INFRA_UART_O1>;
		status = "disabled";
	};

	uart2: serial@11000200 {
		compatible = "mediatek,hsuart";
		reg = <0 0x11000200 0 0x100>;
		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>;
		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
				  <&infracfg_ao CK_INFRA_MUX_UART2_SEL>;
		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
					 <&infracfg_ao CK_INFRA_UART_O2>;
		status = "disabled";
	};

	i2c0: i2c@11003000 {
		compatible = "mediatek,mt7988-i2c",
			     "mediatek,mt7981-i2c";
		reg = <0 0x11003000 0 0x1000>,
		      <0 0x10217080 0 0x80>;
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
		clock-div = <1>;
		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c1: i2c@11004000 {
		compatible = "mediatek,mt7988-i2c",
			     "mediatek,mt7981-i2c";
		reg = <0 0x11004000 0 0x1000>,
		      <0 0x10217100 0 0x80>;
		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
		clock-div = <1>;
		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c2: i2c@11005000 {
		compatible = "mediatek,mt7988-i2c",
			     "mediatek,mt7981-i2c";
		reg = <0 0x11005000 0 0x1000>,
		      <0 0x10217180 0 0x80>;
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
		clock-div = <1>;
		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	pwm: pwm@10048000 {
		compatible = "mediatek,mt7988-pwm";
		reg = <0 0x10048000 0 0x1000>;
		#pwm-cells = <2>;
		clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>,
			 <&infracfg_ao CK_INFRA_66M_PWM_HCK>,
			 <&infracfg_ao CK_INFRA_66M_PWM_CK1>,
			 <&infracfg_ao CK_INFRA_66M_PWM_CK2>,
			 <&infracfg_ao CK_INFRA_66M_PWM_CK3>,
			 <&infracfg_ao CK_INFRA_66M_PWM_CK4>,
			 <&infracfg_ao CK_INFRA_66M_PWM_CK5>,
			 <&infracfg_ao CK_INFRA_66M_PWM_CK6>,
			 <&infracfg_ao CK_INFRA_66M_PWM_CK7>,
			 <&infracfg_ao CK_INFRA_66M_PWM_CK8>;
		clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
			      "pwm4","pwm5","pwm6","pwm7","pwm8";
		status = "disabled";
	};

	snand: snand@11001000 {
		compatible = "mediatek,mt7988-snand",
			     "mediatek,mt7986-snand";
		reg = <0 0x11001000 0 0x1000>,
		      <0 0x11002000 0 0x1000>;
		reg-names = "nfi", "ecc";
		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg_ao CK_INFRA_SPINFI>,
			 <&infracfg_ao CK_INFRA_NFI>,
			 <&infracfg_ao CK_INFRA_66M_NFI_HCK>;
		clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
		assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
				  <&topckgen CK_TOP_NFI1X_SEL>;
		assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
					 <&topckgen CK_TOP_CB_M_D8>;
		status = "disabled";
	};

	spi0: spi@1100a000 {
		compatible = "mediatek,ipm-spi";
		reg = <0 0x11007000 0 0x100>;
		clocks = <&spi_clk>,
			 <&spi_clk>;
		clock-names = "sel-clk", "spi-clk";
		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	spi1: spi@1100b000 {
		compatible = "mediatek,ipm-spi";
		reg = <0 0x11008000 0 0x100>;
		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	spi2: spi@11009000 {
		compatible = "mediatek,ipm-spi";
		reg = <0 0x11009000 0 0x100>;
		clocks = <&spi_clk>,
			 <&spi_clk>;
		clock-names = "sel-clk", "spi-clk";
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	mmc0: mmc@11230000 {
		compatible = "mediatek,mt7988-mmc",
			     "mediatek,mt7986-mmc";
		reg = <0 0x11230000 0 0x1000>;
		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg_ao_cgs CK_INFRA_MSDC400>,
			 <&infracfg_ao_cgs CK_INFRA_MSDC2_HCK>,
			 <&infracfg_ao_cgs CK_INFRA_133M_MSDC_0_HCK>,
			 <&infracfg_ao_cgs CK_INFRA_66M_MSDC_0_HCK>;
		clock-names = "source", "hclk", "source_cg", "axi_cg";
		status = "disabled";
	};

	ethdma: syscon@15000000 {
		compatible = "mediatek,mt7988-ethdma", "syscon";
		reg = <0 0x15000000 0 0x20000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	ethwarp: syscon@15031000 {
		compatible = "mediatek,mt7988-ethwarp", "syscon";
		reg = <0 0x15031000 0 0x1000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	eth: ethernet@15100000 {
		compatible = "mediatek,mt7988-eth", "syscon";
		reg = <0 0x15100000 0 0x20000>;
		mediatek,ethsys = <&ethdma>;
		mediatek,sgmiisys = <&sgmiisys0>;
		mediatek,usxgmiisys = <&usxgmiisys0>;
		mediatek,xfi_pextp = <&xfi_pextp0>;
		mediatek,xfi_pll = <&xfi_pll>;
		mediatek,infracfg = <&topmisc>;
		mediatek,toprgu = <&watchdog>;
		resets = <&ethdma ETHDMA_FE_RST>, <&ethwarp ETHWARP_GSW_RST>;
		reset-names = "fe", "mcm";
		#address-cells = <1>;
		#size-cells = <0>;
		mediatek,mcm;
		status = "disabled";
	};
};