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2021-11-04watchdog: Automatically register device with sysresetSamuel Holland3-0/+39
Add an option to automatically register watchdog devices with the wdt_reboot driver for use with sysreset. This allows sysreset to be a drop-in replacement for platform-specific watchdog reset code, without needing any device tree changes. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-04sysreset: watchdog: Move watchdog reference to plat dataSamuel Holland1-8/+8
Currently, the wdt_reboot driver always gets its watchdog device reference from an OF node. This prevents selecting a watchdog at runtime. Move the watchdog device reference to the plat data, so the driver can be bound with the reference pre-provided. The reference will still be acquired from the OF node if it is not already provided. Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-04sysreset: Mark driver probe functions as staticSamuel Holland4-4/+4
These driver probe functions are not (and should not be) called from outside the respective driver source files. Therefore, the functions should be marked static. Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-04sysreset: Add uclass Kconfig dependency to driversSamuel Holland1-2/+2
None of the sysreset drivers do anything beyond providing sysreset uclass ops. They should depend on the sysreset uclass. Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-03Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini1-0/+1
- usb: mtu3: flush cache for the first GPD when allocate GPD ring
2021-11-03usb: mtu3: flush cache for the first GPD when allocate GPD ringChunfeng Yun1-0/+1
When allocate the GPD ring, and tell its address to the controller, then the driver starts or resumes the QMU, the controller will try to access the first GPD, so need flush the first one to avoid wrong GPD status. Reported-by: Xin Lin <Xin.Lin@mediatek.com> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2021-11-03arm: a37xx: pci: Program the data strobe for config read requestsPali Rohár1-0/+3
According to the Armada 3720 Functional Specification Data Strobe applies for both read and write config requests. Data strobe bits configure which bytes from the start address should be returned for read request. Set value 0xf (all 4 bits) into Data Strobe register to read all four bytes from specified 32-bit config space register. Same value for Data Strobe register is programmed by Linux pci-aardvark.c driver for config read requests. Without this patch pci-aardvark driver sets data strobe register only during config write operations. So any followup config read operations could result with just partial datai returned (if previous write operation was not 32-bit wide). This patch fixes it and ensures that config read operations always read all bytes from requested register. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-03pci: pci_mvebu: Fix comment about driver class namePali Rohár1-1/+1
This is a pci driver, not an eth driver. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-03pci: pci_mvebu: Setup PCI controller to Root Complex modePali Rohár1-0/+6
Root Complex should be the default mode, let's set it explicitly. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-03pci: pci_mvebu: Do not automatically enable bus mastering on PCI BridgePali Rohár1-8/+0
Now that PCI Bridge is working, U-Boot's CONFIG_PCI_PNP code automatically enables memory access and bus mastering when it is needed. So do not prematurely enable memory access and bus mastering. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-03pci: pci_mvebu: Fix place of link up detectionPali Rohár1-10/+4
PCI Bridge is always accessible also when link is down. So move detection of link up from mvebu_pcie_of_to_plat() function to mvebu_pcie_valid_addr() function which is used when accessing PCI config space. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-03pci: pci_mvebu: Remove unused functionsPali Rohár1-16/+0
Functions mvebu_pcie_get_local_bus_nr() and mvebu_pcie_get_local_dev_nr() are not used, so remove them. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-03pci: pci_mvebu: Properly configure and use PCI Bridge (PCIe Root Port)Pali Rohár1-35/+164
The mysterious "Memory controller" PCI device which is present in PCI config space is improperly configured and crippled PCI Bridge which acts as PCIe Root Port for endpoint PCIe card. This PCI Bridge reports in PCI config space incorrect Class Code (Memory Controller) and incorrect Header Type (Type 0). It looks like HW bug in mvebu PCIe controller but apparently it can be changed via mvebu registers to correct values. The worst thing is that this PCI Bridge is crippled and its PCI config registers in range 0x10-0x34 alias access to internal mvebu registers which have different functionality as PCI Bridge registers. Moreover, configuration of PCI primary and secondary bus numbers (registers 0x18 and 0x19) is done via totally different mvebu registers via totally strange method and cannot be done via PCI Bridge config space. Due to above fact about PCI config range 0x10-0x34, allocate a private cfgcache[] buffer in the driver, to which PCI config access requests to the 0x10-0x34 space will be redirected in mvebu_pcie_read_config() and mvebu_pcie_write_config() functions. Function mvebu_pcie_write_config() will also catch writes to PCI_PRIMARY_BUS (0x18) and PCI_SECONDARY_BUS (0x19) registers and set PCI Bridge primary and secondary bus numbers via mvebu's own method. Also, Expansion ROM Base Address register (0x38) is available, but at different offset 0x30. So recalculate register offset before accessing PCI config space. After these steps U-Boot sees working PCI Bridge and CONFIG_PCI_PNP code can finally start enumerating all PCIe devices correctly, even with more complicated PCI topology. So update also mvebu_pcie_valid_addr() function to reflect state of the real device topology. Each PCIe port is de-facto isolated and every PCI Bridge which is part of PCIe Root Complex is also isolated, so put them on separate PCI buses as (local) device 0. U-Boot already supports enumerating separate PCI buses, real (HW) bus number can be retrieved by "PCI_BUS(bdf) - dev_seq(bus)" code, so update config read/write functions to properly handle more complicated tree topologies (e.g. when a PCIe switch with multiple PCI buses is connected to the PCIe port). Local bus number and local device number on mvebu are used for determining which config request type is used (Type 0 vs Type 1). On normal non-broken PCIe hardware it is done by primary and secondary bus numbers. So correctly translate settings between these numbers to ensure that correct config requests are sent over the PCIe bus. As bus numbers are correctly re-configured, it does not make sense to print some initial bogus configuration during probe, so remove this debug code. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-03pci: pci_mvebu: Fix read_config() with PCI_SIZE_8 or PCI_SIZE_16Pali Rohár1-2/+15
When reading 8 or 16 bits from config space, use appropriate readb() or readw() calls. This ensures that PCIe controller does not read more bits from endpoint card as asked by read_config() function. Technically there should not be an issue with reading data from config space which are not later used as there are no clear-by-read registers. But it is better to use correct read operation based on requested size. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-03pci: pci_mvebu: Fix write_config() with PCI_SIZE_8 or PCI_SIZE_16Pali Rohár1-2/+13
Current implementation of write_config() is broken for PCI_SIZE_8 or PCI_SIZE_16 as it always uses writel(), which means that write operation is always 32-bit, so upper 24 bits for PCI_SIZE_8 and upper 16 bits for PCI_SIZE_16 are cleared. Fix this by using writeb() and writew(), respectively. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-31Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini1-0/+1
- usb_mass_storage, xhci-brcm bugfixes
2021-10-31SoC: exynos: add support for exynos 78x0Dzmitry Sankouski4-0/+129
Samsung Exynos 7880 \ 7870 - SoC for mainstream smartphones and tablets introduced on March 2017. Features: - 8 Cortex A53 cores - ARM Mali-T830 MP3 GPU - LTE Cat. 7 (7880) or 6 (7870) modem Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
2021-10-31pinctrl: exynos: add support for multiple pin banksDzmitry Sankouski1-6/+22
Iterate all pin banks to find a pin Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
2021-10-31serial: samsung: add support for skip debug init in s5pDzmitry Sankouski1-0/+3
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
2021-10-31pinctrl: qcom: add pinctrl and gpio drivers for SDM845 SoCDzmitry Sankouski2-3/+6
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stephan Gerhold <stephan@gerhold.net> [trini: Add CONFIG_SDM845 around sdm845_data usage]
2021-10-31spmi: msm: add arbiter version 5 supportDzmitry Sankouski1-50/+104
Currently driver supports only version 1 and 2. Version 5 has slightly different registers structure Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Tom Rini <trini@konsulko.com>
2021-10-31serial: qcom: add support for GENI serial driverDzmitry Sankouski3-0/+632
Generic Interface (GENI) Serial Engine (SE) based uart can be found on newer qualcomm SOCs, starting from SDM845. Tested on Samsung SM-G9600(starqltechn) by chain-loading u-boot with stock bootloader. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Tom Rini <trini@konsulko.com>
2021-10-31iommu: Add Apple DART driverMark Kettenis3-0/+70
The DART is an IOMMU that is used on Apple's M1 SoC. This driver configures the DART such that it operates in bypass mode which is enough to support DMA for the USB3 ports integrated on the SoC. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-31serial: s5p: Add Apple M1 supportMark Kettenis2-24/+84
Apple M1 SoCs include an S5L UART which is a variant of the S5P UART. Add support for this variant and enable it by default on Apple SoCs. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-31test: Add tests for IOMMU uclassMark Kettenis2-0/+20
Add a set of tests for the IOMMU uclass. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-31iommu: Add IOMMU uclassMark Kettenis6-0/+76
This uclass is intended to manage IOMMUs on systems where the IOMMUs are not in bypass mode by default. In that case U-Boot cannot ignore the IOMMUs if it wants to use devices that need to do DMA and sit behind such an IOMMU. This initial IOMMU uclass implementation does not implement and device ops and is intended for IOMMUs that have a bypass mode that does not require address translation. Support for IOMMUs that do require address translation is planned and device ops will be defined when support for such IOMMUs will be added. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-30usb: xhci-brcm: Include header file needed for dev_errStefan Agner1-0/+1
dev_err seems to be moved to different header file. Include dm/device_compat.h file to compile properly. Fixes: 69dae8902b16 ("linux/compat.h: Remove redefinition of dev_xxx macros") Signed-off-by: Stefan Agner <stefan@agner.ch>
2021-10-29mmc: arm_pl180_mmci: Enable HWFC for specific versions of MCIUsama Arif2-0/+15
There are 4 registers (PERIPHID{0-3}) that contain the ID of MCI. For MMCs' with peripheral id 0x02041180 and 0x03041180, H/W flow control needs to be enabled for multi block writes (MMC CMD 18). Signed-off-by: Usama Arif <usama.arif@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-10-29mmc: Fix mmc_switch excessive timeoutKirill Kapranov1-2/+2
Fix branching to avoid premature falling back on a long timeout instead of continuation of the initialization attempt. Clear of the comment to avoid the ambiguity. Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Ye Li <ye.li@nxp.com> Reviewed-by: Marek Behún <marek.behun@nic.cz> Tested-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-10-29drivers: mmc: Add wait_dat0 support for sdhci driverStephen Carlson1-0/+20
Adds an implementation of the wait_dat0 MMC operation for the DM SDHCI driver, allowing the driver to continue when the card is ready rather than waiting for the worst case time on each MMC switch operation. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-10-29drivers: mmc: Add wait_dat0 support for Freescale eSDHC driverStephen Carlson1-0/+16
Adds an implementation of the wait_dat0 MMC operation for the Freescale eSHDC driver, allowing the driver to continue when the card is ready rather than waiting for the worst case time on each MMC switch operation. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-10-26dfu: Sort Kconfig entries alphabeticallyMarek Vasut1-7/+7
The DFU_MTD Kconfig entry is in the wrong position, move it into the correct alphabetically sorted position. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Lukasz Majewski <lukma@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-10-25dfu: dfu_sf: Read the SPI flash in 16 MiB chunksMarek Vasut1-2/+12
Not all SPI flashes and controllers can do continuous transfer longer than 16 MiB, so perform the DFU read in 16 MiB chunks. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Lukasz Majewski <lukma@denx.de> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2021-10-25mmc: sunxi: conditionally include MMC2 initialization codeIcenowy Zheng1-0/+2
Allwinner R329 has no MMC2. Only include the code of MMC2 if the base address of it is defined. Signed-off-by: Icenowy Zheng <icenowy@sipeed.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25watchdog: Add a driver for the sunxi watchdogSamuel Holland3-0/+197
This driver supports the sun4i/sun6i/sun20i watchdog timers. They have a maximum timeout of 16 seconds. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25clk: sunxi: Extend DM_RESET selection to SPLSamuel Holland1-0/+1
The sunxi clock driver exposes a reset controller, so it selects the reset controller framework. Ensure that dependency is also satisfied when building the driver for the SPL. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25power: pmic: axp: Implement poweroff via sysresetSamuel Holland2-1/+50
The AXP PMICs have the ability to power off the system. The existing code for this is duplicated for each PMIC variant, and uses the legacy non-DM "pmic_bus" interface. When SYSRESET is enabled, this can all be replaced with a sysreset device using the DM_PMIC interface. Since the trigger bit is the same on all PMIC variants, use the register definitions from the oldest supported PMIC. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25power: axp: Avoid do_poweroff conflict with sysresetSamuel Holland6-1/+11
The sysreset uclass has an option to provide the do_poweroff() function. When that option is enabled, the AXP power drivers should not provide their own definition. For the AXP305, which is paired with 64-bit systems where TF-A provides PSCI, there is another possible conflict with the PSCI firmware driver. This driver can be enabled even if CONFIG_PSCI_RESET is disabled, so make sure to use the right symbol in the condition. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25phy: sun4i-usb: Support VBUS detection via power supplySamuel Holland2-0/+8
The device tree binding provides for getting VBUS state from a device referenced by phandle, as an optional alternative to using a GPIO. In U-Boot, where there is no power supply class, this VBUS detection will be implemented using a regulator device and its get_enable method. Let's hook this up to the PHY driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25phy: sun4i-usb: Refactor VBUS detection to match LinuxSamuel Holland1-13/+12
The Linux driver checks the VBUS detection GPIO first; then VBUS power supply; then finally assumes VBUS is present. When adding VBUS power supply support, we want to match that order, so we get the same behavior in case both a GPIO and a power supply are provided in the device tree. So refactor the function a bit to remove the early return, and use the same "assume VBUS is present" final fallback. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25phy: sun4i-usb: Remove a couple of debug messagesSamuel Holland1-4/+0
Both of these messages log the GPIO number of the ID detection GPIO, which is not terribly useful, especially in the VBUS detection function. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-23Merge https://source.denx.de/u-boot/custodians/u-boot-spiTom Rini13-85/+147
- Fix mtd erase with mtdpart (Marek Behún) - NXP fspi driver fixes (Kuldeep Singh)
2021-10-23spi: nxp_fspi: Implement errata workaround for LS1028AKuldeep Singh1-5/+48
Errata ERR050568 description says that "Flash access by FlexSPI AHB command may not work with platform frequency equal to 300 MHz" on LS1028A. By default, smaller length reads(equal to RX FIFO size) are done by IP bus and larger length reads using AHB bus. For adding errata workaround, use IP bus to read entire flash contents and disable AHB path when platform frequency is 300Mhz. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-23spi: nxp-fspi: Add support for IP read onlyKuldeep Singh1-4/+20
Add support for disabling AHB bus and read entire flash contents via IP bus only. Please note, this enables IP bus read using a quirk which can be enabled directly in device-type data or in existence of an errata where AHB bus may need to be disabled. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-23mtd: spi-nor-ids: Add SECT_4K to mt25qu512aKris Chaplin1-1/+1
The mt25qu512a supports 4K or 64K sectors, so adding SECT_4K to enable 4K sector usage. Tested on Intel n5x hardware with QSPI carrier card Signed-off-by: Kris Chaplin <kris.chaplin@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> [jagan: droped Tested-by of patch author and datasheet link] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-23mtd: spi-nor-ids: Add is25lp512 and is25wp512 devicesKris Chaplin1-0/+4
Add is25lp512 and is25wp512 devices to spi-nor id table Tested on Intel n5x hardware with QSPI carrier card Signed-off-by: Kris Chaplin <kris.chaplin@linux.intel.com> [jagan: droped Tested-by of patch author] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-23mtd: Remove mtd_erase_callback() entirelyMarek Behún10-68/+2
The original purpose of mtd_erase_callback() in Linux at the time it was imported to U-Boot, was to inform the caller that erasing is done (since it was an asynchronous operation). All supplied callback methods in U-Boot do nothing, but the mtd_erase_callback() function was (until previous patch) grossly abused in U-Boot's mtdpart implementation for completely different purpose. Since we got rid of the abusement, remove the mtd_erase_callback() function and the .callback member from struct erase_info entirely, in order to avoid such problems in the future. Signed-off-by: Marek Behún <marek.behun@nic.cz>
2021-10-23mtd: mtdpart: Make mtdpart's _erase method saneMarek Behún1-8/+18
The _erase() method of the mtdpart driver, part_erase(), currently implements offset shifting (for given mtdpart partition) in a weird way: 1. part_erase() adds partition offset to block address 2. parent driver's _erase() method is called 3. parent driver's _erase() method calls mtd_erase_callback() 4. mtd_erase_callback() subtracts partition offset from block address so that the callback function is given correct address The problem here is that if the parent's driver does not call mtd_erase_callback() in some scenario (this was recently a case for spi_nor_erase(), which did not call mtd_erase_callback() at all), the offset is not shifted back. Moreover the code would be more readable if part_erase() not only added partition offset before calling parent's _erase(), but also subtracted it back afterwards. Currently the mtd_erase_callback() is expected to do this subtracting since it does have to do it anyway. Add the more steps to this procedure: 5. mtd_erase_callback() adds partition offset to block address so that it returns the the erase_info structure members as it received them 6. part_erase() subtracts partition offset from block address This makes the code more logical and also prevents errors in case parent's driver does not call mtd_erase_callback() for some reason. (BTW, the purpose of mtd_erase_callback() in Linux is to inform the caller that it is done, since in Linux erasing is done asynchronously. We are abusing the purpose of mtd_erase_callback() in U-Boot for completely different purpose. The callback function itself has empty implementation in all cases in U-Boot.) Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-10-23mtd: spi-nor-core: Check for ctrlc() in spi_nor_erase()Marek Behún1-0/+5
May it possible to interrupt the spi_nor_erase() function. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-10-23mtd: spi-nor-core: Call mtd_erase_callback() from spi_nor_erase()Marek Behún1-2/+18
The spi_nor_erase() function does not call mtd_erase_callback() as it should. The mtdpart code currently implements the subtraction of partition offset in mtd_erase_callback(). This results in partition offset being added prior calling spi_nor_erase(), but not subtracted back on return. The result is that the `mtd erase` command does not erase the whole partition, only some of it's blocks: => mtd erase "Rescue system" Erasing 0x00000000 ... 0x006fffff (1792 eraseblock(s)) jedec_spi_nor spi-nor@0: at 0x100000, len 4096 jedec_spi_nor spi-nor@0: at 0x201000, len 4096 jedec_spi_nor spi-nor@0: at 0x302000, len 4096 jedec_spi_nor spi-nor@0: at 0x403000, len 4096 jedec_spi_nor spi-nor@0: at 0x504000, len 4096 jedec_spi_nor spi-nor@0: at 0x605000, len 4096 jedec_spi_nor spi-nor@0: at 0x706000, len 4096 This is obviously wrong. Add proper calling of mtd_erase_callback() into the spi_nor_erase() function. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org> Reported-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
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