SoC: exynos: add support for exynos 78x0

Samsung Exynos 7880 \ 7870 - SoC for mainstream smartphones and tablets
introduced on March 2017.
Features:
- 8 Cortex A53 cores
- ARM Mali-T830 MP3 GPU
- LTE Cat. 7 (7880) or 6 (7870) modem

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>

4 files changed, 129 insertions, 0 deletions

diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index 76f35ac5d9..06ed585f3d 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -357,6 +357,7 @@ static const struct udevice_id exynos_gpio_ids[] = {
 	{ .compatible = "samsung,exynos4x12-pinctrl" },
 	{ .compatible = "samsung,exynos5250-pinctrl" },
 	{ .compatible = "samsung,exynos5420-pinctrl" },
+	{ .compatible = "samsung,exynos78x0-gpio" },
 	{ }
 };
 
diff --git a/drivers/pinctrl/exynos/Kconfig b/drivers/pinctrl/exynos/Kconfig
index 84b6aaae09..a60f49869b 100644
--- a/drivers/pinctrl/exynos/Kconfig
+++ b/drivers/pinctrl/exynos/Kconfig
@@ -8,3 +8,11 @@ config PINCTRL_EXYNOS7420
 	help
 	  Support pin multiplexing and pin configuration control on
 	  Samsung's Exynos7420 SoC.
+
+config PINCTRL_EXYNOS78x0
+	bool "Samsung Exynos78x0 pinctrl driver"
+	depends on ARCH_EXYNOS && PINCTRL_FULL
+	select PINCTRL_EXYNOS
+	help
+	  Support pin multiplexing and pin configuration control on
+	  Samsung's Exynos78x0 SoC.
diff --git a/drivers/pinctrl/exynos/Makefile b/drivers/pinctrl/exynos/Makefile
index 6a14a474bf..07db970ca9 100644
--- a/drivers/pinctrl/exynos/Makefile
+++ b/drivers/pinctrl/exynos/Makefile
@@ -5,3 +5,4 @@
 
 obj-$(CONFIG_PINCTRL_EXYNOS)		+= pinctrl-exynos.o
 obj-$(CONFIG_PINCTRL_EXYNOS7420)	+= pinctrl-exynos7420.o
+obj-$(CONFIG_PINCTRL_EXYNOS78x0)	+= pinctrl-exynos78x0.o
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos78x0.c b/drivers/pinctrl/exynos/pinctrl-exynos78x0.c
new file mode 100644
index 0000000000..01e9a4fede
--- /dev/null
+++ b/drivers/pinctrl/exynos/pinctrl-exynos78x0.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Exynos78x0 pinctrl driver.
+ *
+ * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com)
+ *
+ * based on drivers/pinctrl/exynos/pinctrl-exynos7420.c :
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <fdtdec.h>
+#include <asm/arch/pinmux.h>
+#include "pinctrl-exynos.h"
+
+static struct pinctrl_ops exynos78x0_pinctrl_ops = {
+	.set_state	= exynos_pinctrl_set_state
+};
+
+/* pin banks of exynos78x0 pin-controller 0 (ALIVE) */
+static struct samsung_pin_bank_data exynos78x0_pin_banks0[] = {
+	EXYNOS_PIN_BANK(6, 0x000, "etc0"),
+	EXYNOS_PIN_BANK(3, 0x020, "etc1"),
+	EXYNOS_PIN_BANK(8, 0x040, "gpa0"),
+	EXYNOS_PIN_BANK(8, 0x060, "gpa1"),
+	EXYNOS_PIN_BANK(8, 0x080, "gpa2"),
+	EXYNOS_PIN_BANK(5, 0x0a0, "gpa3"),
+	EXYNOS_PIN_BANK(2, 0x0c0, "gpq0"),
+};
+
+/* pin banks of exynos78x0 pin-controller 1 (CCORE) */
+static struct samsung_pin_bank_data exynos78x0_pin_banks1[] = {
+	EXYNOS_PIN_BANK(2, 0x000, "gpm0"),
+};
+
+/* pin banks of exynos78x0 pin-controller 2 (DISPAUD) */
+static struct samsung_pin_bank_data exynos78x0_pin_banks2[] = {
+	EXYNOS_PIN_BANK(4, 0x000, "gpz0"),
+	EXYNOS_PIN_BANK(6, 0x020, "gpz1"),
+	EXYNOS_PIN_BANK(4, 0x040, "gpz2"),
+};
+
+/* pin banks of exynos78x0 pin-controller 4 (FSYS) */
+static struct samsung_pin_bank_data exynos78x0_pin_banks4[] = {
+	EXYNOS_PIN_BANK(3, 0x000, "gpr0"),
+	EXYNOS_PIN_BANK(8, 0x020, "gpr1"),
+	EXYNOS_PIN_BANK(2, 0x040, "gpr2"),
+	EXYNOS_PIN_BANK(4, 0x060, "gpr3"),
+	EXYNOS_PIN_BANK(6, 0x080, "gpr4"),
+};
+
+/* pin banks of exynos78x0 pin-controller 6 (TOP) */
+static struct samsung_pin_bank_data exynos78x0_pin_banks6[] = {
+	EXYNOS_PIN_BANK(4, 0x000, "gpb0"),
+	EXYNOS_PIN_BANK(3, 0x020, "gpc0"),
+	EXYNOS_PIN_BANK(4, 0x040, "gpc1"),
+	EXYNOS_PIN_BANK(4, 0x060, "gpc4"),
+	EXYNOS_PIN_BANK(2, 0x080, "gpc5"),
+	EXYNOS_PIN_BANK(4, 0x0a0, "gpc6"),
+	EXYNOS_PIN_BANK(2, 0x0c0, "gpc8"),
+	EXYNOS_PIN_BANK(2, 0x0e0, "gpc9"),
+	EXYNOS_PIN_BANK(7, 0x100, "gpd1"),
+	EXYNOS_PIN_BANK(6, 0x120, "gpd2"),
+	EXYNOS_PIN_BANK(8, 0x140, "gpd3"),
+	EXYNOS_PIN_BANK(7, 0x160, "gpd4"),
+	EXYNOS_PIN_BANK(5, 0x180, "gpd5"),
+	EXYNOS_PIN_BANK(3, 0x1a0, "gpe0"),
+	EXYNOS_PIN_BANK(4, 0x1c0, "gpf0"),
+	EXYNOS_PIN_BANK(2, 0x1e0, "gpf1"),
+	EXYNOS_PIN_BANK(2, 0x200, "gpf2"),
+	EXYNOS_PIN_BANK(4, 0x220, "gpf3"),
+	EXYNOS_PIN_BANK(5, 0x240, "gpf4"),
+};
+
+struct samsung_pin_ctrl exynos78x0_pin_ctrl[] = {
+	{
+		/* pin-controller instance 0 Alive data */
+		.pin_banks	= exynos78x0_pin_banks0,
+		.nr_banks	= ARRAY_SIZE(exynos78x0_pin_banks0),
+	}, {
+		/* pin-controller instance 1 CCORE data */
+		.pin_banks	= exynos78x0_pin_banks1,
+		.nr_banks	= ARRAY_SIZE(exynos78x0_pin_banks1),
+	}, {
+		/* pin-controller instance 2 DISPAUD data */
+		.pin_banks	= exynos78x0_pin_banks2,
+		.nr_banks	= ARRAY_SIZE(exynos78x0_pin_banks2),
+	}, {
+		/* pin-controller instance 4 FSYS data */
+		.pin_banks	= exynos78x0_pin_banks4,
+		.nr_banks	= ARRAY_SIZE(exynos78x0_pin_banks4),
+	}, {
+		/* pin-controller instance 6 TOP data */
+		.pin_banks	= exynos78x0_pin_banks6,
+		.nr_banks	= ARRAY_SIZE(exynos78x0_pin_banks6),
+	},
+	{/* list terminator */}
+};
+
+static const struct udevice_id exynos78x0_pinctrl_ids[] = {
+	{ .compatible = "samsung,exynos78x0-pinctrl",
+		.data = (ulong)exynos78x0_pin_ctrl },
+	{ }
+};
+
+U_BOOT_DRIVER(pinctrl_exynos78x0) = {
+	.name		= "pinctrl_exynos78x0",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= exynos78x0_pinctrl_ids,
+	.priv_auto = sizeof(struct exynos_pinctrl_priv),
+	.ops		= &exynos78x0_pinctrl_ops,
+	.probe		= exynos_pinctrl_probe,
+};