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path: root/drivers/spi
AgeCommit message (Expand)AuthorFilesLines
2022-12-22sandbox: Finish migration to KconfigTom Rini1-0/+10
2022-12-05arm: Remove unused mx27 codeTom Rini1-8/+0
2022-12-05global: Move remaining CONFIG_SYS_* to CFG_SYS_*Tom Rini2-4/+4
2022-12-05spi: cadence-qspi: Remove condition for calling enable linear modeAshok Reddy Soma1-5/+1
2022-12-05spi: zynqmp_qspi: Add support for 64-bit read/writeVenkatesh Yadav Abbarapu1-2/+4
2022-12-05spi: zynqmp_gqspi: Update tapdelay valueT Karthik Reddy1-1/+1
2022-11-22spi: cadence-qspi: Fix compilation error in mini u-boot flash resetAshok Reddy Soma1-2/+2
2022-11-22qspi: versal-net: Add condition for tapdelay registerAshok Reddy Soma1-1/+2
2022-11-10global: Migrate CONFIG_SYS_MPC8* symbols to the CFG_SYS namespaceTom Rini1-1/+1
2022-11-10mediatek: Include <linux/sizes.h> where neededTom Rini1-0/+1
2022-11-03Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini3-0/+512
2022-11-03spi: Add Microchip PolarFire SoC QSPI driverPadmarao Begari3-0/+512
2022-11-02Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi.gitTom Rini3-0/+232
2022-10-31arm: bcmbca: replace ARCH_BCM6858 symbols in Kconfig with BCM6858William Zhang1-2/+1
2022-10-31arm: bcmbca: replace ARCH_BCM68360 symbols in Kconfig with BCM6856William Zhang1-1/+1
2022-10-31arm: bcmbca: replace ARCH_BCM63158 symbols in Kconfig with BCM63158William Zhang1-1/+1
2022-10-27spi: nuvoton: add NPCM PSPI controller driverJim Liu3-0/+232
2022-10-16spi: Implement spi_set_speedPaul Barker1-0/+15
2022-10-07spi: zynqmp_qspi: Mark zynqmp_qspi_set_tapdelay() as staticVenkatesh Yadav Abbarapu1-1/+1
2022-09-26Merge tag 'xilinx-for-v2023.01-rc1-v2' of https://gitlab.denx.de/u-boot/custo...Tom Rini3-3/+5
2022-09-26spi: zynqmp_gqspi: Add support for Versal NETMichal Simek1-1/+2
2022-09-26spi: cadence_qspi: Add support for Versal NET platformMichal Simek2-2/+3
2022-09-23spi: add support for MediaTek spi-mem controllerWeijie Gao3-0/+710
2022-09-19Merge branch 'master' into nextTom Rini1-7/+2
2022-09-18cyclic: Use schedule() instead of WATCHDOG_RESET()Stefan Roese3-3/+3
2022-09-13spi: aspeed: Clock frequency adjustment supportChin-Ting Kuo1-10/+186
2022-09-13spi: aspeed: Support customized decoded address rangesChin-Ting Kuo1-9/+127
2022-09-13spi: aspeed: Adjust decoded range size supportChin-Ting Kuo1-1/+143
2022-09-13spi: aspeed: SPI dirmap read supportChin-Ting Kuo1-0/+88
2022-09-13spi-mem: Add dirmap API from LinuxChin-Ting Kuo2-0/+278
2022-09-13spi: aspeed: Support AST2400 platformChin-Ting Kuo1-7/+98
2022-09-13spi: aspeed: Add ASPEED SPI controller driverChin-Ting Kuo3-0/+612
2022-09-13spi: zynqmp_qspi: Code alignmentAshok Reddy Soma1-12/+6
2022-09-13spi: zynqmp_gqspi: Fix issue of reading more than 32bits lengthAshok Reddy Soma1-23/+39
2022-09-13spi: zynqmp_gqspi: Add support for IO modeAshok Reddy Soma1-5/+76
2022-09-13spi: zynqmp_gqspi: Add tap delays for VersalAshok Reddy Soma1-22/+38
2022-09-13spi: cadence-qspi: Use priv instead of plat across the driverAshok Reddy Soma4-204/+236
2022-09-13spi: cadence_qspi: Call read_setup for STIG_READAshok Reddy Soma1-1/+6
2022-09-13spi: cadence-qspi: Correct flash reset function nameAshok Reddy Soma1-2/+2
2022-09-02renesas: Fix RPC-IF compatible valuesGeert Uytterhoeven1-7/+2
2022-07-26spi: zynq_qspi: Fix programming qspi speedAshok Reddy Soma1-6/+3
2022-07-26spi: zynq_qspi: Add support for zynq_qspi_mem_exec_opAshok Reddy Soma1-0/+42
2022-07-26spi: zynq_qspi: Use dummy buswidth in dummy byte calculationT Karthik Reddy1-2/+8
2022-07-26spi: zynq_qspi: Add child pre probe functionSiva Durga Prasad Paladugu1-0/+12
2022-07-26spi: xilinx_spi: Add support ops to axi qspi driverT Karthik Reddy1-1/+45
2022-07-26spi: xilinx_spi: Add support for spi memory operationsT Karthik Reddy1-78/+116
2022-07-18spi: sunxi: Add support for F1C100s SPI controllerAndre Przywara1-0/+9
2022-07-18spi: sunxi: improve SPI clock calculationAndre Przywara1-4/+7
2022-07-18spi: sunxi: refactor SPI speed/mode programmingAndre Przywara1-43/+52
2022-07-18spi: sunxi: use XCH status to detect in-progress transferIcenowy Zheng1-9/+5