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2022-09-18clk: imx: Add initial support for i.MXRT1170 clock driverJesse Taube3-0/+238
Add clock driver support for i.MXRT1170. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
2022-09-18clk: imx: Add i.MXRT11xx pllv3 variantJesse Taube2-3/+54
The i.MXRT11 series has two new pll types but are variants of existing. This patch adds the ability to read one of the pll types' frequency as it can't be changed unlike the generic pll it also has the division factors swapped. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
2022-09-08Merge tag 'u-boot-stm32-20220907' of ↵Tom Rini1-15/+20
https://source.denx.de/u-boot/custodians/u-boot-stm - simplify the STM32MP15x package parsing code - remove test on CONFIG_DM_REGULATOR in stm32mp1 board and enable CONFIG_DM_REGULATOR for stm32f769-disco - handle ck_usbo_48m clock provided by USBPHYC to fix the command 'usb start' after alignment with Linux kernel v5.19 DT (clocks = <&usbphyc>) - Fix SYS_HZ_CLOCK value for stih410-b2260 board - Switch STMM32MP15x DHSOM to FMC2 EBI driver - Remove hwlocks from pinctrl in STM32MP15x to avoid issue with kernel
2022-09-06Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini2-11/+11
2022-09-06clk: stm32mp: handle ck_usbo_48m clock provided by USBPHYCPatrick Delaunay1-15/+20
Handle the input clock of RCC USB_PHY_48, provided by USBPHYC and named "ck_usbo_48m". Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-09-06dt-bindings: clock: sifive: sync FU740 PRCI clock binding headerIcenowy Zheng2-11/+11
This commit sychronizes the header file for FU740 PRCI clocks with the one from Linux 5.19. The constant values are the same, but all constant names are changed (most are just prefixed with FU740_). Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-09-04clk: rockchip: rk3399: Fix Unknown clock 77 on mmc@fe310000Michal Suchanek1-23/+43
Adding some debug prints I can see: MMC: mmc@fe320000: Got clock clock-controller@ff760000 76 mmc@fe310000: Got clock clock-controller@ff760000 77 Unknown clock 77 rockchip_dwmmc_get_mmc_clk: err=-2 mmc@fe310000: 3, mmc@fe320000: 1, mmc@fe330000: 0 According to kernel code the SDIO clock is identical to SDMMC clock except for the con 16->15 change. Add support for the clock to avoid the error. Signed-off-by: Michal Suchanek <msuchanek@suse.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-07-21treewide: Fix Marek's name and change my e-mail addressMarek Behún2-2/+2
Fix diacritics in some instances of my name and change my e-mail address to kabel@kernel.org. Add corresponding .mailmap entries. Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-18reset: sunxi: Reuse the platform data from the clock driverSamuel Holland1-1/+6
The clock and reset drivers use the exact same platform data. Simplify them by sharing the object. This is safe because the parent device (the clock device) always gets its driver model callbacks run first. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-07-18clk: sunxi: Convert driver private data to platform dataSamuel Holland1-17/+24
All of the driver private data should really be platform data since it is determined statically (selected by the compatible string or extracted from the devicetree). Move everything to platform data, so it can be provided when binding the driver. This is useful for SPL, or for instantiating the driver as part of an MFD. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-07-18clk: sunxi: Use a single driver for all variantsSamuel Holland16-276/+137
Now that all of the variants use the same bind/probe functions and ops, there is no need to have a separate driver for each variant. Since most SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit of firmware size and RAM. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-07-18reset: sunxi: Get the reset count from the CCU descriptorSamuel Holland16-95/+20
This allows all of the clock drivers to use a common bind function. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-07-18clk: sunxi: Prevent out-of-bounds gate array accessSamuel Holland1-2/+5
Because the gate arrays are not given explicit sizes, the arrays are only as large as the highest-numbered gate described in the driver. However, only a subset of the CCU clocks are needed by U-Boot. So there are valid clock specifiers with indexes greater than the size of the arrays. Referencing any of these clocks causes out-of-bounds access. Fix this by checking the identifier against the size of the array. Fixes: 0d47bc705651 ("clk: Add Allwinner A64 CLK driver") Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-07-18clk: sunxi: Store the array sizes in the CCU descriptorSamuel Holland15-0/+32
The reset array size is currently used for bounds checking in the reset driver. The same bounds check should really be done in the clock driver. Currently, the array size is provided to the reset driver separately from the CCU descriptor, which is a bit strange. Let's do this the usual way, with the array sizes next to the arrays themselves. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-07-13clk: mtmips: add clock driver for MediaTek MT7621 SoCWeijie Gao2-0/+289
This patch adds a clock driver for MediaTek MT7621 SoC. This driver provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-07-11Merge branch 'next'Tom Rini11-30/+95
2022-07-06clk/ast2500: Add SD clockJoel Stanley1-0/+23
In order to use the clock from the sdhci driver, add the SD clock. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06clk/ast2600: Adjust eMMC clock namesJoel Stanley1-2/+2
Adjust clock to stay compatible with those used by the Linux kernel device tree. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06clk/aspeed: Add debug message when clock failsJoel Stanley2-2/+5
A common message across platforms that prints the clock number. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-01drivers: clk: Update license for Intel N5X deviceTeik Heng Chong4-8/+8
All the source code of clk-mem-n5x.c and clk-n5x.c are from Intel, update the license to use both GPL2.0 and BSD-3 Clause because this copy of code may used for open source and internal project. Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-26clk: sunxi: Add additional RTC compatible stringsSamuel Holland1-0/+2
Compatible strings for some new RTC hardware variants were added to the binding. Add them to the driver in preparation for supporting those new SoCs. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-06-23clk: scmi: support SCMI multi-channelEtienne Carriere1-7/+26
Update SCMI clock driver to get its assigned SCMI channel during initialization. This change allows SCMI clock protocol to use a dedicated channel when defined in the DT. The reference is saved in SCMI clock driver private data. Cc: Lukasz Majewski <lukma@denx.de> Cc: Sean Anderson <seanga2@gmail.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23firmware: scmi: prepare scmi uclass API to multi-channelEtienne Carriere1-5/+5
Changes SCMI driver API function devm_scmi_process_msg() to add an SCMI channel reference argument for when SCMI agent supports SCMI protocol specific channels. First argument of devm_scmi_process_msg() is also change to point to the caller SCMI protocol device rather than its parent device (the SCMI agent device). The argument is a pointer to opaque struct scmi_channel known from the SCMI transport drivers. It is currently unused and caller a pass NULL value. A later change will enable such support once SCMI protocol drivers have means to get the channel reference during initialization. Cc: Lukasz Majewski <lukma@denx.de> Cc: Sean Anderson <seanga2@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-20Merge branch 'master' into nextTom Rini1-4/+4
Merge in v2022.07-rc5.
2022-06-17clk: Add directory for STM32 clock driversPatrick Delaunay7-19/+33
Add a directory in drivers/clk to regroup the clock drivers for all STM32 Soc with CONFIG_ARCH_STM32 (MCUs with cortex M) or CONFIG_ARCH_STM32MP (MPUs with cortex A). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Grzegorz Szymaszek <gszymaszek@short.pl> Acked-by: Sean Anderson <seanga2@gmail.com> Change-Id: I955af307963f732167396f0157a30cf2fc91f150
2022-06-14clk: imx8mp: use usb_core_ref for usb_root_clkAndrey Zhizhikin1-1/+1
Upstream commit 7a2c3be95a50 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock") added usb_core_ref for USB Controller but never set it to be used as a clock source, using rather "osc_32k" instead. This produces following boot log message: "clk_register: failed to get osc_32k device (parent of usb_root_clk)" Fix the USB controller clock source by using usb_core_ref instead of osc_32k. Fixes: 7a2c3be95a50 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-14clk: imx8mp: fix root clock names for ecspiAndrey Zhizhikin1-3/+3
Root clock name contained underscore, which does not match to the actual clock name. Correct the name to match what is present in the FDT. Fixes: 87f958810fcb ("clk: imx8mp: Add ECSPI clocks") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: uboot-imx <uboot-imx@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-10arm: mach-k3: am62: Introduce autogenerated SoC dataSuman Anna1-0/+6
Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-05-24clk: sunxi: add and use dummy gate clocksAndre Przywara4-0/+9
Some devices enumerate various clocks in their DT, and many drivers just blanketly try to enable all of them. This creates problems since we only model a few gate clocks, and the clock driver outputs a warning when a clock is not described: ========= sunxi_set_gate: (CLK#3) unhandled ========= Some clocks don't have an enable bit, or are already enabled in a different way, so we might want to just ignore them. Add a CCU_CLK_F_DUMMY_GATE flag that indicates that case, and define a GATE_DUMMY macro that can be used in the clock description array. Define a few clocks, used by some pinctrl devices, that way to suppress the runtime warnings. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-05-24clk: sunxi: add PIO bus gate clocksAndre Przywara12-0/+28
The introduction of the DM pinctrl driver made its probe function enable all clocks enumerated in the DT. This includes the "CLK_BUS_PIO" (and variations) gate clock. Also CLK_PLL_PERIPH0 is used by the R_CCU device. So far we didn't describe those clocks in our clock driver. As we enable them already in the SPL, the devices happen to work, but the clock driver still complains about not finding those clocks: ========= sunxi_set_gate: (CLK#58) unhandled ========= Add the one-liners that are needed to announce the gate bit for those clocks, to silence that message on the console. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-05-24clk: sunxi: h6_r: Correct the driver nameSamuel Holland1-2/+2
H6 is from the sun50i family, not sun6i. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-23clk: sunxi: implement clock driver for suniv f1c100sGeorge Hilliard3-0/+82
The f1c100s has a clock tree similar to those of other sunxi parts. Add support for it. Signed-off-by: George Hilliard <thirtythreeforty@gmail.com> Signed-off-by: Yifan Gu <me@yifangu.com> Acked-by: Sean Anderson <seanga2@gmail.com> [Andre: add PIO and I2C] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-10clk: stm32mp1: Add missing newlineMarek Vasut1-1/+1
Add missing newline to this debug message, no functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-05clk: scmi: fix scmi_clk_get_attibute()Heinrich Schuchardt1-5/+3
Local variable out.name lives on the stack and therefore cannot be returned directly. Move the strdup() call into the function. (Coverity 352460) Fixes: 7c33f78983c3 ("clk: scmi: register scmi clocks with CCF") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-05-05clk: nuvoton: Add support for NPCM750Jim Liu5-0/+502
Add clock controller driver for NPCM750 Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-05-02vpl: Add Kconfig options for VPLSimon Glass1-0/+26
Add VPL versions of commonly used Kconfig options. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-04-25clk: meson: update driver for g12a-ao clocksVyacheslav Bocharov1-6/+9
Update g12a-ao clk driver: - move clk->id check to .request function - remove unnecessary check (gate->reg == 0) Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220424082159.757622-4-adeep@lexina.in
2022-04-25clk: meson: fix driver name for g12a-ao clocksVyacheslav Bocharov1-1/+1
Update the clk-g12a-ao driver from "axg" to "g12a" Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220424082159.757622-3-adeep@lexina.in
2022-04-25clk: meson: add minimal driver for axg-ao clocksVyacheslav Bocharov2-0/+87
Add minimal driver AO clocks on meson AXG family. Only ADC related clocks are supported. Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220424082159.757622-2-adeep@lexina.in
2022-04-18rockchip: rk3066: add clock driver for rk3066 socPaweł Jarosz2-0/+718
Add the clock driver for the rk3066 platform. Derived from the rk3288 and rk3188 driver it supports only a bare minimum to bring up the system to reduce the TPL size for: SDRAM clock configuration. The boot devices NAND, EMMC, SDMMC, SPI. A UART for the debug messages (fixed) at 115200n8. A SARADC for the recovery button. A TIMER for the delays (fixed). There's support for two possible frequencies, the safe 600MHz which will work with default pmic settings and will be set to get away from the 24MHz default and the maximum of 1.416Ghz, which boards can set if they were able to get pmic support for it. After the clock tree is set during the TPL probe there's no parent update support. In OF_REAL mode the drivers ns16550.c and dw-apb-timer.c obtain the (fixed) clk_get_rate from the clock driver instead of platdata. The rk3066 cru node has a number of assigned-clocks properties that call the .set_rate() function. Add them to the list so that they return a 0 instead of -ENOENT. Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-04-18rockchip: clk: add clocks to px30_clk_enableChris Morgan1-0/+3
Add the HCLK_OTG, HCLK_SFC, and SCLK_SFC clocks to px30_clk_enable. Without this change U-Boot reports an error of "Enable clock-controller@ff2b0000 failed" on boot when using the SFC or USB in U-Boot. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-04-13clk: imx8mp: Fix 24M and 32k clockMarek Vasut1-1/+11
Fix registration of 24M and 32k clock, those got applied or rebased incorrectly, so fill in the correct code. Fixes: 7a2c3be95a5 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com>
2022-04-12clk: imx8mp: Add ECSPI clocksElmar Albert1-1/+18
Add clock tables required for bing up ECSPI interfaces Signed-off-by: Elmar Albert <ealbert@data-modul.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: uboot-imx <uboot-imx@nxp.com> Signed-off-by: Elmar Albert <ealbert@data-modul.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-04-12clk: imxrt: Use dts for anatop base addressJesse Taube2-2/+2
In Linux IMX and IMXRT use the device tree to hold the anatop address. The anatop is used in clock drivers as it controls the internal PLLs This will move the macro from asm/arch-imxrt to the device tree. This presumably should also be done with the other IMX boards as well. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
2022-04-12clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clockMarek Vasut1-0/+20
Add clock tables required to bring up DWC3 USB, USB PHY and HSIOMIX domain. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2022-04-12clk: imx8m: reduce rate table duplicationAngus Ainslie6-218/+91
Re-factor the imx8m[nmpq] rate tables into the common pll1416x clock driver. 43cdaa1567ad3 ("clk: imx8mm: Move 1443X/1416X PLL clock structure to common place") Signed-off-by: Angus Ainslie <angus@akkea.ca> Tested-by: Adam Ford <aford173@gmail.com> #imx8mm-beacon
2022-04-12clk: imx8mq: Add a clock driver for the imx8mqAngus Ainslie3-0/+570
This is a DM clock driver based off the imx8mm u-boot driver and the linux kernel driver. All of the PLLs and clocks are initialized so the subsystems below are functional and tested. 1) USB host and peripheral 2) ECSPI 3) UART 4) I2C all busses 5) USDHC for eMMC support 6) USB storage 7) GPIO 8) DRAM Signed-off-by: Angus Ainslie <angus@akkea.ca> Acked-by: Sean Anderson <seanga2@gmail.com>
2022-04-12clk: imx8mm: add pwm clocks supportTommaso Merciai1-0/+28
Add clocks support for the PWM controllers. This is ported from Linux v5.17-rc8. Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
2022-04-05Merge tag 'xilinx-for-v2022.07-rc1-v2' of ↵Tom Rini1-0/+7
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.07-rc1 v2 xilinx: - Allow booting bigger kernels till 100MB zynqmp: - DT updates (reset IDs) - Remove unneeded low level uart initialization from psu_init* - Enable PWM features - Add support for 1EG device serial_zynq: - Change fifo behavior in DEBUG mode zynq_sdhci: - Fix BASECLK setting calculation clk_zynqmp: - Add support for showing video clock gpio: - Update slg driver to handle DT flags net: - Update ethernet_id code to support also DM_ETH_PHY - Add support for DM_ETH_PHY in gem driver - Enable dynamic mode for SGMII config in gem driver pwm: - Add driver for cadence PWM versal: - Add support for reserved memory firmware: - Handle PD enabling for SPL - Add support for IOUSLCR SGMII configurations include: - Sync phy.h with Linux - Update xilinx power domain dt binding headers
2022-04-05clk: zynqmp: Add support for for DP audio/video clocksMichal Simek1-0/+7
Add support for getting rate for DP audio and video clocks. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/8792efe1fd9715f7c8a2e1e24f0454fb5b25d833.1648552434.git.michal.simek@xilinx.com
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 17:27:28 +0000