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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2021-07-26clk: zynqmp: Add support for enabling clock on lpd_lsbusMichal Simek1-0/+1
2021-07-17Merge tag 'u-boot-imx-20210717' of https://gitlab.denx.de/u-boot/custodians/u...Tom Rini1-1/+22
2021-07-16Merge branch '2021-07-15-assorted-fixes'Tom Rini1-1/+5
2021-07-16clk: stm32mp1: add support of SYSCFG clockPatrick Delaunay1-0/+1
2021-07-15clk: Detect failure to set defaultsSimon Glass1-1/+5
2021-07-14clk: uniphier: Add PCIe clock entryKunihiko Hayashi1-0/+3
2021-07-10clk: imx8mm: Add SPI clocksFrieder Schrempf1-1/+22
2021-07-08clk: armada-37xx: Set DM_FLAG_PRE_RELOCMarek Behún2-0/+2
2021-07-07Merge tag 'dm-pull-6jul21' of https://source.denx.de/u-boot/custodians/u-boot-dmTom Rini1-0/+2
2021-07-06dm: define LOG_CATEGORY for all uclassPatrick Delaunay1-0/+2
2021-07-06drivers: clk: sifive: fu740-prci: replace 'pciaux' with 'pcieaux'Green Wan1-3/+3
2021-07-01Merge tag 'xilinx-for-v2021.10' of https://source.denx.de/u-boot/custodians/u...Tom Rini3-0/+198
2021-06-28Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-sh int...Tom Rini7-0/+371
2021-06-28Merge tag 'v2021.07-rc5' into nextTom Rini1-2/+6
2021-06-24clk: renesas: Add R8A779A0 clock tablesHai Pham7-0/+338
2021-06-24clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock codeMarek Vasut2-0/+33
2021-06-23clk: zynq: Add clock wizard driverZhengxun3-0/+198
2021-06-19Merge tag 'u-boot-rockchip-20210618' of https://source.denx.de/u-boot/custodi...Tom Rini2-0/+2960
2021-06-18clk: cosmetic change in uclassPatrick Delaunay1-1/+1
2021-06-18rockchip: rk3568: add clock driverElaine Zhang2-0/+2960
2021-06-17clk: k210: Move k210 clock out of its own subdirectorySean Anderson5-15/+14
2021-06-17clk: k210: Remove bypass driverSean Anderson2-274/+1
2021-06-17clk: k210: Don't set PLL rates if we are already at the correct rateSean Anderson1-7/+8
2021-06-17clk: k210: Re-add support for setting rateSean Anderson1-5/+84
2021-06-17clk: k210: Implement soc_clk_dumpSean Anderson1-2/+66
2021-06-17clk: k210: Move pll into the rest of the driverSean Anderson3-594/+601
2021-06-17clk: k210: Rewrite to remove CCFSean Anderson3-523/+439
2021-06-17clk: Allow force setting clock defaults before relocationSean Anderson2-11/+18
2021-06-11clk: add support for TI K3 SoC clocksTero Kristo3-0/+387
2021-06-11clk: add support for TI K3 SoC PLLTero Kristo3-0/+296
2021-06-11clk: fix set_rate to clean up cached rates for the hierarchyTero Kristo1-0/+19
2021-06-11clk: fix assigned-clocks to pass with deferring providerTero Kristo1-0/+18
2021-06-11clk: sci-clk: fix return value of set_rateTero Kristo1-2/+4
2021-06-11clk: do not attempt to fetch clock pointer with null deviceTero Kristo1-0/+2
2021-06-11clk: fixed_rate: add API for directly registering fixed rate clocksTero Kristo1-0/+45
2021-06-09clk: imx: clk-imxrt1050: introduce IMXRT1050_CLK_USBOH3Giulio Benetti1-0/+2
2021-06-09clk: imx: clk-imxrt1050: introduce LCDIF_PIX and rename LCDIF to LCDIF_APBGiulio Benetti1-2/+4
2021-05-31drivers: clk: add fu740 supportGreen Wan8-753/+1286
2021-05-24treewide: Convert macro and uses of __section(foo) to __section("foo")Marek Behún1-2/+2
2021-05-21clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handlingMarek Vasut1-43/+43
2021-05-21clk: renesas: Add register pointers into struct cpg_mssr_infoHai Pham3-45/+65
2021-05-21clk: renesas: Introduce enum clk_reg_layoutHai Pham1-0/+6
2021-05-21clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable()Hai Pham4-6/+8
2021-05-21clk: renesas: Make reset controller modemr register offset configurableMarek Vasut20-5/+21
2021-05-21clk: renesas: Add support for RPCD2 clockHai Pham2-5/+17
2021-05-21clk: renesas: Fix Realtime Module Stop Control Register offsetsHai Pham1-1/+1
2021-05-21clk: renesas: Fix incorrect return RPC clk_get_rateHai Pham1-1/+1
2021-05-21clk: renesas: Reinstate RPC clock on R-Car D3/E3Marek Vasut2-0/+18
2021-05-21clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12Marek Vasut7-163/+212
2021-05-21clk: renesas: Synchronize R-Car Gen2 tables with Linux 5.12Marek Vasut5-9/+6
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